Abstract: In an aspect of the disclosure, a class D power amplifier with an overcurrent protection (OCP) circuit is provided. The class D power amplifier includes a plurality of output transistors, and the OCP circuit is mirrored to at least one output transistor of the plurality of output transistors in a closed-loop feedback configuration for precisely controlling a sensing current of the OCP circuit with respect to an output current of the at least one output transistor. The class D power amplifier with the OCP circuit in the closed-loop feedback configuration mitigates a variation in a current threshold value for triggering interruption of the class D power amplifier.

Abstract: Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.

Abstract: A class D power amplifier is provided. The class D power amplifier includes a class D driver circuit having a plurality of output transistors, at least one active clamp circuit coupled to at least one output transistor of the plurality of output transistors, and at least one filter bank circuit coupled to the at least one active clamp circuit for controlling a voltage of the at least one output transistor. Accordingly, a voltage across a drain node and source node (VDS), a voltage across a gate node and source node (VGS), and a voltage across the gate node and drain node (VGD) of the output transistors is reduced to increase reliability of the power amplifier while consuming less power and utilizing less die area.

Abstract: Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element.

Abstract: A class D power amplifier is provided. The class D power amplifier includes a class D driver circuit having a plurality of output transistors, at least one active clamp circuit coupled to at least one output transistor of the plurality of output transistors, and at least one filter bank circuit coupled to the at least one active clamp circuit for controlling a voltage of the at least one output transistor. Accordingly, a voltage across a drain node and source node (VDS), a voltage across a gate node and source node (VGS), and a voltage across the gate node and drain node (VGD) of the output transistors is reduced to increase reliability of the power amplifier while consuming less power and utilizing less die area.

Abstract: In an aspect of the disclosure, a class D power amplifier with an overcurrent protection (OCP) circuit is provided. The class D power amplifier includes a plurality of output transistors, and the OCP circuit is mirrored to at least one output transistor of the plurality of output transistors in a closed-loop feedback configuration for precisely controlling a sensing current of the OCP circuit with respect to an output current of the at least one output transistor. The class D power amplifier with the OCP circuit in the closed-loop feedback configuration mitigates a variation in a current threshold value for triggering interruption of the class D power amplifier.

Abstract: Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.

Abstract: Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element.

Abstract: A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.

Abstract: An operational amplifier and a method for amplifying a signal. Embodiments provide a convenient and effective mechanism for reducing die area, design time and design verification time by sharing compensation components between the common-mode and differential feedback networks of the operational amplifier. As such, fewer compensation components are required, thereby reducing component die area. Additionally, given that the compensation components are shared between the common-mode and differential feedback networks, the feedback networks can be stabilized together with fewer compensation components to specify and verify, thereby reducing design and design verification time. Further, embodiments provide a compensation component coupling which does not couple directly to virtual ground, thereby reducing the noise of the operational amplifier.

Abstract: A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.

Abstract: A driver circuit, system, and method is provided. The driver circuit includes a plurality of delay cells or circuits, each comprising a set of flip-flop circuits coupled in series to produce a staged set of outputs onto an output port of the driver circuit. The staged outputs are sequentially applied to the output port at a time depending on the number of flip-flop circuits within each stage. The number of such circuits can be programmably modified so that the slew rate output of the driver circuit can be programmably changed. The driver circuit can be a low speed driver circuit clocked by a low speed clocking signal of, for example, 1.5 MHz, with the slew rate derived by a clocking signal of, for example, 480 MHz. The higher speed clocking signal clocks the flip-flop circuits, yet the output is staged so that the low speed driver circuit transitions between logic states using the higher speed clock, but at a must slower edge rate.

Abstract: An improved amplifier circuit is provided herein with a gain stage and a bias stage, which may be switchably connected to the gain stage during power-up operations. The bias stage reduces a power-up time associated with the gain stage, while minimizing current consumption in the next amplifier stage and improving battery life. For example, during power-up, the bias stage may enable the output voltage of the gain stage to gradually rise from a ground potential to a desired common mode level in a highly controlled and predictable manner. By preventing “glitches” in the output voltage, the bias stage eliminates the need for inserting switches in the signal path between the output nodes of the gain stage and input nodes of the next amplifier stage.