Patents by Inventor Matthew David Conrad

Matthew David Conrad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006491
    Abstract: Silicon carbide (SiC) materials including SiC wafers and SiC boules and related methods are disclosed that provide large dimension SiC wafers with reduced crystallographic stress. Growth conditions for SiC materials include maintaining a generally convex growth surface of SiC crystals, adjusting differences in front-side to back-side thermal profiles of growing SiC crystals, supplying sufficient source flux to allow commercially viable growth rates for SiC crystals, and reducing the inclusion of contaminants or non-SiC particles in SiC source materials and corresponding SiC crystals. By forming larger dimension SiC crystals that exhibit lower crystallographic stress, overall dislocation densities that are associated with missing or additional planes of atoms may be reduced, thereby improving crystal quality and usable SiC crystal growth heights.
    Type: Application
    Filed: September 9, 2024
    Publication date: January 2, 2025
    Inventors: Yuri Khlebnikov, Varad R. Sakhalkar, Caleb A. Kent, Valeri F. Tsvetkov, Michael J. Paisley, Oleksandr Kramarenko, Matthew David Conrad, Eugene Deyneka, Steven Griffiths, Simon Bubel, Adrian R. Powell, Robert Tyler Leonard, Elif Balkas, Curt Progl, Michael Fusco, Alexander Shveyd, Kathy Doverspike, Lukas Nattermann
  • Publication number: 20240352622
    Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Inventors: Yuri Khlebnikov, Varad R. Sakhalkar, Caleb A. Kent, Valeri F. Tsvetkov, Michael J. Paisley, Oleksandr Kramarenko, Matthew David Conrad, Eugene Deyneka, Steven Griffiths, Simon Bubel, Adrian R. Powell, Robert Tyler Leonard, Elif Balkas, Jeffrey C. Seaman
  • Patent number: 12125701
    Abstract: Silicon carbide (SiC) materials including SiC wafers and SiC boules and related methods are disclosed that provide large dimension SiC wafers with reduced crystallographic stress. Growth conditions for SiC materials include maintaining a generally convex growth surface of SiC crystals, adjusting differences in front-side to back-side thermal profiles of growing SiC crystals, supplying sufficient source flux to allow commercially viable growth rates for SiC crystals, and reducing the inclusion of contaminants or non-SiC particles in SiC source materials and corresponding SiC crystals. By forming larger dimension SiC crystals that exhibit lower crystallographic stress, overall dislocation densities that are associated with missing or additional planes of atoms may be reduced, thereby improving crystal quality and usable SiC crystal growth heights.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: October 22, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Yuri Khlebnikov, Varad R. Sakhalkar, Caleb A. Kent, Valeri F. Tsvetkov, Michael J. Paisley, Oleksandr Kramarenko, Matthew David Conrad, Eugene Deyneka, Steven Griffiths, Simon Bubel, Adrian R. Powell, Robert Tyler Leonard, Elif Balkas, Curt Progl, Michael Fusco, Alexander Shveyd, Kathy Doverspike, Lukas Nattermann
  • Publication number: 20240332352
    Abstract: A method of analyzing semiconductor wafers includes capturing a first image of a first crystalline material, etching a first surface of the first crystalline material to delineate etch defects in the first crystalline material, and capturing a second image of first crystalline material after etching the first surface of the first crystalline material. Based on the second image, labels of etch defects delineated in the first surface of the first crystalline material are generated. The first image and the labels of etch defects are spatially coordinated to form a defect map identifying one or more defects in the first image based on the delineated etch defects, and based on the defect map and nondestructive data obtained from a second crystalline material, defects in the second crystalline material are identified.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Inventors: Robert Tyler Leonard, Matthew David Conrad, Edward Robert Van Brunt
  • Patent number: 12054850
    Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: August 6, 2024
    Assignee: WOLFSPEED, INC.
    Inventors: Yuri Khlebnikov, Varad R. Sakhalkar, Caleb A. Kent, Valeri F. Tsvetkov, Michael J. Paisley, Oleksandr Kramarenko, Matthew David Conrad, Eugene Deyneka, Steven Griffiths, Simon Bubel, Adrian R. Powell, Robert Tyler Leonard, Elif Balkas, Jeffrey C. Seaman
  • Patent number: 12040355
    Abstract: Nondestructive characterization of crystalline wafers is provided, including defect detection, identification, and counting. Certain aspects relate to development of nondestructive, high fidelity defect characterization and/or dislocation counting methods based on deep neural networks. Certain aspects relate to nondestructive methods for defect characterization of silicon carbide (SiC) wafers. By subjecting SiC wafers to nondestructive defect characterization, SiC wafers in their final state may be characterized and subsequently used for device fabrication, vastly reducing the expense of the characterization process. Nondestructive defect characterization also allows for increased sampling and improved feedback loops between crystalline growth process development and subsequent device production.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: July 16, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Robert Tyler Leonard, Matthew David Conrad, Edward Robert Van Brunt
  • Publication number: 20220189768
    Abstract: Silicon carbide (SiC) materials including SiC wafers and SiC boules and related methods are disclosed that provide large dimension SiC wafers with reduced crystallographic stress. Growth conditions for SiC materials include maintaining a generally convex growth surface of SiC crystals, adjusting differences in front-side to back-side thermal profiles of growing SiC crystals, supplying sufficient source flux to allow commercially viable growth rates for SiC crystals, and reducing the inclusion of contaminants or non-SiC particles in SiC source materials and corresponding SiC crystals. By forming larger dimension SiC crystals that exhibit lower crystallographic stress, overall dislocation densities that are associated with missing or additional planes of atoms may be reduced, thereby improving crystal quality and usable SiC crystal growth heights.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 16, 2022
    Inventors: Yuri Khlebnikov, Varad R. Sakhalkar, Caleb A. Kent, Valeri F. Tsvetkov, Michael J. Paisley, Oleksandr Kramarenko, Matthew David Conrad, Eugene Deyneka, Steven Griffiths, Simon Bubel, Adrian R. Powell, Robert Tyler Leonard, Elif Balkas, Curt Progl, Michael Fusco, Alexander Shveyd, Kathy Doverspike, Lukas Nattermann
  • Patent number: 11361454
    Abstract: Wafer images and related alignment methods for crystalline wafers are disclosed. Certain aspects relate to accessing and aligning images of a same or similar crystalline wafer captured from different imaging sources. Alignment may include determining spatial differences between shared crystalline features in various wafer images of the same or similar crystalline wafer and transforming at least one of the images according to the determined spatial differences. With sufficient alignment, information may be associated and/or transferred between the various images, thereby providing the capability of forming a combined wafer image and sub-images thereof with high resolution and spatial coordination between different image sources. Certain aspects relate to development of nondestructive, high fidelity defect characterization and/or dislocation counting methods in crystalline materials based on modern deep convolutional neural networks (DCNN).
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 14, 2022
    Assignee: WOLFSPEED, INC.
    Inventors: Robert Tyler Leonard, Matthew David Conrad, Edward Robert Van Brunt
  • Publication number: 20210272298
    Abstract: Wafer images and related alignment methods for crystalline wafers are disclosed. Certain aspects relate to accessing and aligning images of a same or similar crystalline wafer captured from different imaging sources. Alignment may include determining spatial differences between shared crystalline features in various wafer images of the same or similar crystalline wafer and transforming at least one of the images according to the determined spatial differences. With sufficient alignment, information may be associated and/or transferred between the various images, thereby providing the capability of forming a combined wafer image and sub-images thereof with high resolution and spatial coordination between different image sources. Certain aspects relate to development of nondestructive, high fidelity defect characterization and/or dislocation counting methods in crystalline materials based on modern deep convolutional neural networks (DCNN).
    Type: Application
    Filed: February 28, 2020
    Publication date: September 2, 2021
    Inventors: Robert Tyler Leonard, Matthew David Conrad, Edward Robert Van Brunt
  • Publication number: 20210198804
    Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.
    Type: Application
    Filed: December 17, 2020
    Publication date: July 1, 2021
    Inventors: Yuri Khlebnikov, Varad R. Sakhalkar, Caleb A. Kent, Valeri F. Tsvetkov, Michael J. Paisley, Oleksandr Kramarenko, Matthew David Conrad, Eugene Deyneka, Steven Griffiths, Simon Bubel, Adrian R. Powell, Robert Tyler Leonard, Elif Balkas, Jeffrey C. Seaman
  • Publication number: 20200365685
    Abstract: Nondestructive characterization of crystalline wafers is provided, including defect detection, identification, and counting. Certain aspects relate to development of nondestructive, high fidelity defect characterization and/or dislocation counting methods based on deep neural networks. Certain aspects relate to nondestructive methods for defect characterization of silicon carbide (SiC) wafers. By subjecting SiC wafers to nondestructive defect characterization, SiC wafers in their final state may be characterized and subsequently used for device fabrication, vastly reducing the expense of the characterization process. Nondestructive defect characterization also allows for increased sampling and improved feedback loops between crystalline growth process development and subsequent device production.
    Type: Application
    Filed: January 23, 2020
    Publication date: November 19, 2020
    Inventors: Robert Tyler Leonard, Matthew David Conrad, Edward Robert Van Brunt