Patents by Inventor Matthew David PIERSON
Matthew David PIERSON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11422938Abstract: A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.Type: GrantFiled: October 15, 2019Date of Patent: August 23, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew David Pierson, Kai Chirca, Timothy David Anderson
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Publication number: 20220229779Abstract: A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.Type: ApplicationFiled: April 6, 2022Publication date: July 21, 2022Inventors: Kai CHIRCA, Matthew David PIERSON
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Patent number: 11347644Abstract: A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.Type: GrantFiled: October 15, 2019Date of Patent: May 31, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kai Chirca, Daniel Wu, Matthew David Pierson
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Patent number: 11341052Abstract: A device includes an interconnect and a plurality of devices connected to the interconnect. The plurality of devices includes a first interface connected to the interconnect and a second interface connected to the interconnect. The plurality of devices further includes a first memory bank connected to the interconnect and a second memory bank connected to the interconnect. The plurality of devices further includes an external memory interface connected to the interconnect and a controller configured to establish virtual channels among the plurality of devices connected to the interconnect.Type: GrantFiled: October 15, 2019Date of Patent: May 24, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kai Chirca, Matthew David Pierson, Timothy David Anderson, Joseph Zbiciak
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Publication number: 20220156192Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Kai Chirca, Matthew David Pierson, David E. Smith, Timothy David Anderson
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Patent number: 11307988Abstract: A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.Type: GrantFiled: October 15, 2019Date of Patent: April 19, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kai Chirca, Matthew David Pierson
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Patent number: 11237968Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.Type: GrantFiled: October 15, 2019Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kai Chirca, Matthew David Pierson, David E. Smith, Timothy David Anderson
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Publication number: 20210382822Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Inventors: Matthew David PIERSON, Daniel WU, Kai CHIRCA
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Publication number: 20210349821Abstract: Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.Type: ApplicationFiled: July 20, 2021Publication date: November 11, 2021Inventors: Kai CHIRCA, Daniel WU, Matthew David PIERSON
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Publication number: 20210326260Abstract: Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Inventors: Kai CHIRCA, Timothy David ANDERSON, Joseph ZBICIAK, David E. SMITH, Matthew David PIERSON
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Patent number: 11099994Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.Type: GrantFiled: October 9, 2020Date of Patent: August 24, 2021Assignee: Texas Instmments IncorporatedInventors: Matthew David Pierson, Daniel Wu, Kai Chirca
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Patent number: 11099993Abstract: Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.Type: GrantFiled: October 15, 2019Date of Patent: August 24, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kai Chirca, Daniel Wu, Matthew David Pierson
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Patent number: 11086778Abstract: Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.Type: GrantFiled: October 15, 2019Date of Patent: August 10, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kai Chirca, Timothy David Anderson, Joseph Zbiciak, David E. Smith, Matthew David Pierson
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Patent number: 10990529Abstract: Techniques for accessing data, comprising receiving a first memory request associated with a first clock domain, converting a first memory address of the first memory request from a first memory address format associated with the first clock domain to a second memory address format associated with the second clock domain, transitioning the first memory request to a second clock domain, creating a first scoreboard entry associated with the first memory request, transmitting the first memory request to a memory based on the converted first memory address, receiving a first response to the first memory request, transitioning the first response to the second clock domain and clearing the first scoreboard entry based on the received response.Type: GrantFiled: October 15, 2019Date of Patent: April 27, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Daniel Wu, Kai Chirca, Matthew David Pierson
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Publication number: 20210026768Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.Type: ApplicationFiled: October 9, 2020Publication date: January 28, 2021Inventors: Matthew David PIERSON, Daniel WU, Kai CHIRCA
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Patent number: 10802974Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.Type: GrantFiled: October 15, 2019Date of Patent: October 13, 2020Assignee: Texas Instruments IncorporatedInventors: Matthew David Pierson, Daniel Wu, Kai Chirca
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Publication number: 20200119753Abstract: A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.Type: ApplicationFiled: October 15, 2019Publication date: April 16, 2020Inventors: Kai CHIRCA, Daniel WU, Matthew David PIERSON
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Publication number: 20200117467Abstract: A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.Type: ApplicationFiled: October 15, 2019Publication date: April 16, 2020Inventors: Kai CHIRCA, Matthew David PIERSON
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Publication number: 20200117603Abstract: A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.Type: ApplicationFiled: October 15, 2019Publication date: April 16, 2020Inventors: Matthew David PIERSON, Kai CHIRCA, Timothy David ANDERSON
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Publication number: 20200117606Abstract: Techniques for accessing data, comprising receiving a first memory request associated with a first clock domain, converting a first memory address of the first memory request from a first memory address format associated with the first clock domain to a second memory address format associated with the second clock domain, transitioning the first memory request to a second clock domain, creating a first scoreboard entry associated with the first memory request, transmitting the first memory request to a memory based on the converted first memory address, receiving a first response to the first memory request, transitioning the first response to the second clock domain and clearing the first scoreboard entry based on the received response.Type: ApplicationFiled: October 15, 2019Publication date: April 16, 2020Inventors: Daniel WU, Kai CHIRCA, Matthew David PIERSON