Abstract: An endpoint processor includes a processor block, a timer block, a memory block, and analog-to-digital converter. The timer block is arranged to provide a time based signal to the processor block. The memory block cooperates with the processor block. The analog-to-digital converter is arranged to provide an interface between an analog signal and the processor block. The analog signal includes encoded data from a power signal. The processor block is arranged to control a sampling rate that is associated with the analog-to-digital converter such that the analog signal is down-converted as an under-sampled signal. The processor block is arranged to extract the encoded data from the down-converted signal by executing a digital signal processing algorithm that is stored in the memory block. The digital signal processing algorithm is arranged to reject fundamental and harmonic frequencies that are associated with a power-line frequency that is associated with the power signal.

Abstract: An endpoint processor includes a processor block, a timer block, a memory block, and analog-to-digital converter. The timer block is arranged to provide a time based signal to the processor block. The memory block cooperates with the processor block. The analog-to-digital converter is arranged to provide an interface between an analog signal and the processor block. The analog signal includes encoded data from a power signal. The processor block is arranged to control a sampling rate that is associated with the analog-to-digital converter such that the analog signal is down-converted as an under-sampled signal. The processor block is arranged to extract the encoded data from the down-converted signal by executing a digital signal processing algorithm that is stored in the memory block. The digital signal processing algorithm is arranged to reject fundamental and harmonic frequencies that are associated with a power-line frequency that is associated with the power signal.

Abstract: An endpoint processor includes a processor block, a timer block, a memory block, and analog-to-digital converter. The timer block is arranged to provide a time based signal to the processor block. The memory block cooperates with the processor block. The analog-to-digital converter is arranged to provide an interface between an analog signal and the processor block. The analog signal includes encoded data from a power signal. The processor block is arranged to control a sampling rate that is associated with the analog-to-digital converter such that the analog signal is down-converted as an under-sampled signal. The processor block is arranged to extract the encoded data from the down-converted signal by executing a digital signal processing algorithm that is stored in the memory block. The digital signal processing algorithm is arranged to reject fundamental and harmonic frequencies that are associated with a power-line frequency that is associated with the power signal.

Abstract: An endpoint in a power distribution system includes a transmitter. The transmitter includes a transformer, a half-bridge driver, a first and second driver, and a resonant circuit. A primary winding from the transformer is coupled to a power distribution line, while the secondary winding is coupled to the transmitter. The half-bridge drive circuit selectively asserts drive signals. The resonant circuit has a natural resonant frequency in an audio frequency range. The half-bridge driver is arranged to selectively activate the first and second drivers such that the power-line is modulated with a square-wave signal at a frequency that is associated with encoded data. The half-bridge driver circuit can also be arranged to provide power to the transmitter, and to the endpoint.

Abstract: An endpoint is configured for communication with a distribution substation. The endpoint includes a receiver conditioning block and a receiver processing block. The receiver conditioning block is positioned downstream from the distribution substation, and arranged to provide an analog signal that is responsive to the power signal from the distribution line. The receiver processing block is configured to extract encoded data from the power signal by under-sampling the analog signal, and processing the under-sampled analog signal such that fundamental and harmonic frequencies associated with the power signal are suppressed. Command signals from the distribution substation are extracted from the power-line. Each endpoint is addressable by an ID code, and is configurable via downstream command signals that are associated with the ID code. The endpoint collects data at demand based and schedule based intervals.