Patents by Inventor Matthew David SINCLAIR

Matthew David SINCLAIR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250103395
    Abstract: A computer-implemented method for dynamic resource management can include evaluating, by at least one processor, whether a priority of one or more processes associated with a request for one or more shared resources meets a threshold condition. The method can additionally include determining, by the at least one processor and in response to an evaluation that the priority meets the threshold condition, whether the one or more shared resources is available to meet the request. The method can further include completing, by the at least one processor and in response to a determination that the one or more shared resources is available, execution of the one or more processes. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Bradford Beckmann, Matthew David Sinclair, Vinay Bharadwaj Ramakrishnaiah, William Peter Ehrett
  • Patent number: 12131199
    Abstract: A processing system monitors and synchronizes parallel execution of workgroups (WGs). One or more of the WGs perform (e.g., periodically or in response to a trigger such as an indication of oversubscription) a waiting atomic instruction. In response to a comparison between an atomic value produced as a result of the waiting atomic instruction and an expected value, WGs that fail to produce a correct atomic value are identified as being in a waiting state (e.g., waiting for a synchronization variable). Execution of WGs in the waiting state is prevented (e.g., by a context switch) until corresponding synchronization variables are released.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: October 29, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexandru Dutu, Matthew David Sinclair, Bradford Beckmann, David A. Wood
  • Publication number: 20240220315
    Abstract: A processing system includes a scheduling mechanism for producing data for fine-grained reordering of workgroups of a kernel to produce blocks of data, such as for communication across devices to enable overlapping of a producer computation with an all-reduce communication across the network. This scheduling mechanism enables a first parallel processor to schedule and execute a set of workgroups of a producer operation to generate data for transmission to a second parallel processor in a desired traffic pattern. At the same time, the second parallel processor schedules and executes a different set of workgroups of the producer operation to generate data for transmission in a desired traffic pattern to a third parallel processor or back to the first parallel processor.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Inventors: Suchita Pati, Shaizeen Aga, Nuwan Jayasena, Matthew David Sinclair
  • Patent number: 11481250
    Abstract: A first workgroup is preempted in response to threads in the first workgroup executing a first wait instruction including a first value of a signal and a first hint indicating a type of modification for the signal. The first workgroup is scheduled for execution on a processor core based on a first context after preemption in response to the signal having the first value. A second workgroup is scheduled for execution on the processor core based on a second context in response to preempting the first workgroup and in response to the signal having a second value. A third context it is prefetched into registers of the processor core based on the first hint and the second value. The first context is stored in a first portion of the registers and the second context is prefetched into a second portion of the registers prior to preempting the first workgroup.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 25, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexandru Dutu, Matthew David Sinclair, Bradford Beckmann, David A. Wood
  • Publication number: 20210373975
    Abstract: A processing system monitors and synchronizes parallel execution of workgroups (WGs). One or more of the WGs perform (e.g., periodically or in response to a trigger such as an indication of oversubscription) a waiting atomic instruction. In response to a comparison between an atomic value produced as a result of the waiting atomic instruction and an expected value, WGs that fail to produce a correct atomic value are identified as being in a waiting state (e.g., waiting for a synchronization variable). Execution of WGs in the waiting state is prevented (e.g., by a context switch) until corresponding synchronization variables are released.
    Type: Application
    Filed: September 23, 2020
    Publication date: December 2, 2021
    Inventors: Alexandru DUTU, Matthew David SINCLAIR, Bradford BECKMANN, David A. WOOD
  • Publication number: 20200167191
    Abstract: A processing system includes a task queue, a laxity-aware task scheduler coupled to the task queue, and a workgroup dispatcher coupled to the laxity-aware task scheduler. Based on a laxity evaluation of laxity values associated with a plurality of tasks stored in the task queue, the workgroup dispatcher schedules the plurality of tasks. The laxity evaluation includes determining a priority of each task of the plurality of tasks. The laxity value is determined using laxity information, where the laxity information includes an arrival time, a task duration, a task deadline, and a number of workgroups.
    Type: Application
    Filed: November 26, 2018
    Publication date: May 28, 2020
    Inventors: Tsung Tai YEH, Bradford BECKMANN, Sooraj PUTHOOR, Matthew David SINCLAIR
  • Publication number: 20200004586
    Abstract: A first workgroup is preempted in response to threads in the first workgroup executing a first wait instruction including a first value of a signal and a first hint indicating a type of modification for the signal. The first workgroup is scheduled for execution on a processor core based on a first context after preemption in response to the signal having the first value. A second workgroup is scheduled for execution on the processor core based on a second context in response to preempting the first workgroup and in response to the signal having a second value. A third context it is prefetched into registers of the processor core based on the first hint and the second value. The first context is stored in a first portion of the registers and the second context is prefetched into a second portion of the registers prior to preempting the first workgroup.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Alexandru DUTU, Matthew David SINCLAIR, Bradford BECKMANN, David A. WOOD