Abstract: The available bandwidth of an Input/Output (I/O) communications link is increased by removing the need for retraining events on a communications link. This results in removing a potentially severe system performance degradation penalty that may occur from data traffic stoppage during the retraining events. The available bandwidth is further increased by removing a timing error which results in increasing a timing margin for other components. This results in an increase in the maximum speed of systems with high speed I/O and communication transceiver Integrated Circuits (IC)s.

Abstract: According to an embodiment of the invention, a method and apparatus for signal modulation are described. According to an embodiment of the invention, a method comprises producing and transferring a modulated signal. The modulation of the signal is over a plurality of amplitude levels, including at least a first amplitude level, a second amplitude level and a third amplitude level, and over a plurality of time slots, including at least a first time slot, a second time slot, and a third time slot. The modulated signal transitions from the first amplitude level to the second amplitude level in the first phase slot, remains at the second amplitude level in the second time slot, and transitions from the second amplitude level to the third amplitude level in a third time slot.

Abstract: A system for aggregating data includes aggregation mechanisms. Each aggregation mechanism is configured to receive data from incoming ports and aggregate timing information for the incoming ports before determining where to route the data from outgoing ports. The system may include line cards. Each line card may be configured to transmit data to the aggregate mechanisms.

Abstract: In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

Abstract: Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.

Abstract: In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

Abstract: A method for integrating population count operations with bit shift operations has been developed. The method can be used for incrementing a pointer by a population count of a sparse vector. The method further provides for balancing the input loads at the inputs of the population count and bit shift circuits so that the execution of operations is more balanced, which, in effect, increases computational speed and efficiency. An apparatus that integrates population count circuitry and bit shift circuitry has also been developed. The apparatus comprises a plurality of dynamic stages followed by static stages. The dynamic stages involve the use of dynamic nodes which represent values dependent upon values of individual bits in the pointer and the sparse vector. The apparatus further allows for an expansion through circuit repetition so that the topology of the apparatus can change according to the size of the pointer and sparse vector.

Abstract: Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.

Abstract: A method for integrating population count operations with bit shift operations has been developed. The method can be used for incrementing a pointer by a population count of a sparse vector. The method further provides for balancing the input loads at the inputs of the population count and bit shift circuits so that the execution of operations is more balanced, which, in effect, increases computational speed and efficiency. An apparatus that integrates population count circuitry and bit shift circuitry has also been developed. The apparatus comprises a plurality of dynamic stages followed by static stages. The dynamic stages involve the use of dynamic nodes which represent values dependent upon values of individual bits in the pointer and the sparse vector. The apparatus further allows for an expansion through circuit repetition so that the topology of the apparatus can change according to the size of the pointer and sparse vector.