Patents by Inventor Matthew E. Fernsler
Matthew E. Fernsler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8027825Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.Type: GrantFiled: May 30, 2008Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: Matthew E. Fernsler, Tilman Gloekler, Sanjay Gupta, Christopher J. Spandikow, Todd Swanson
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Patent number: 8006155Abstract: A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.Type: GrantFiled: January 9, 2007Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Matthew E. Fernsler, Tilman Gloekler, Sanjay Gupta, Christopher J. Spandikow, Todd Swanson
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Patent number: 7900086Abstract: A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.Type: GrantFiled: May 29, 2008Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Ramyanshu Datta, Matthew E. Fernsler, Harm P. Hofstee
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Patent number: 7688930Abstract: A mechanism for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the mechanism, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.Type: GrantFiled: May 29, 2008Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Irene Beattie, Nathan P. Chelstrom, Matthew E. Fernsler, Mack W. Riley
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Patent number: 7620126Abstract: A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.Type: GrantFiled: September 27, 2005Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: David William Boerstler, Matthew E. Fernsler, Eskinder Hailu, Jieming Qi, Mack Wayne Riley
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Patent number: 7590194Abstract: An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.Type: GrantFiled: September 27, 2005Date of Patent: September 15, 2009Assignee: International Business Machines CorporationInventors: David William Boerstler, Matthew E. Fernsler, Eskinder Hailu, Jieming Qi, Mack Wayne Riley
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Patent number: 7562272Abstract: An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.Type: GrantFiled: October 6, 2005Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: Irene Beattie, Nathan P. Chelstrom, Matthew E. Fernsler, Mack W. Riley
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Publication number: 20090089636Abstract: A method, system, and computer program product for identifying failures in multi-core processors, utilizing logic built-in self test (LBIST) technology. Multi-core processors, having LBIST and pseudo-random pattern generator (PRPG) circuitry, are tested. Controlled by the LBIST control logic, PRPG inputs a test pattern into scan chains within the cores of each device. A new test pattern is generated and executed during the scan shift phase of each LBIST loop. Logic output generated by each scan chain in the core is compared to other core logic output. Failures within the multi-core processors are determined by whether the logic output generated from a core, within a latch sequence, does not match the logic output of the other cores. If logic output, from a core within a latch sequence, does not match, then the latch number, loop number, and latch values are recorded as failed.Type: ApplicationFiled: October 1, 2007Publication date: April 2, 2009Inventors: Matthew E. Fernsler, Mack W. Riley, Michael F. Wang
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Publication number: 20080288230Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.Type: ApplicationFiled: May 30, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew E. Fernsler, Tilman Gloekler, Sanjay Gupta, Christopher J. Spandikow, Todd Swanson
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Publication number: 20080225566Abstract: A mechanism for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the mechanism, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.Type: ApplicationFiled: May 29, 2008Publication date: September 18, 2008Applicant: International Business Machines CorporationInventors: Irene Beattie, Nathan P. Chelstrom, Matthew E. Fernsler, Mack W. Riley
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Publication number: 20080229166Abstract: A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.Type: ApplicationFiled: May 29, 2008Publication date: September 18, 2008Applicant: Internaional Business Machines CorporationInventors: Ramyanshu Datta, Matthew E. Fernsler, Harm P. Hofstee
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Publication number: 20080167853Abstract: A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource.Type: ApplicationFiled: January 9, 2007Publication date: July 10, 2008Inventors: Matthew E. Fernsler, Tilman Gloekler, Sanjay Gupta, Christopher J. Spandikow, Todd Swanson
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Publication number: 20070300115Abstract: An apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device are provided. With the apparatus and method, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.Type: ApplicationFiled: June 1, 2006Publication date: December 27, 2007Inventors: Ramyanshu Datta, Matthew E. Fernsler, Harm P. Hofstee