Patents by Inventor Matthew E. Souter

Matthew E. Souter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180082965
    Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 22, 2018
    Applicant: SUSS MicroTec Photonic Systems Inc.
    Inventors: Brian M. Erwin, Brittany L. Hedrick, Nicholas A. Polomoff, TaeHo Kim, Matthew E. Souter
  • Publication number: 20180076160
    Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 15, 2018
    Applicant: SUSS MicroTec Photonic Systems Inc.
    Inventors: Brian M. Erwin, Brittany L. Hedrick, Nicholas A. Polomoff, TaeHo Kim, Matthew E. Souter
  • Patent number: 9754823
    Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: September 5, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SÜSS MICROTEC PHOTONIC SYSTEMS INC.
    Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
  • Patent number: 9748135
    Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: August 29, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SUSS MICROTEC PHOTONIC SYSTEMS INC.
    Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
  • Publication number: 20170117241
    Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Applicant: SUSS MicroTec Photonic Systems Inc.
    Inventors: Brian M. Erwin, Brittany L. Hedrick, Nicholas A. Polomoff, TaeHo Kim, Matthew E. Souter
  • Publication number: 20160204028
    Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.
    Type: Application
    Filed: March 17, 2016
    Publication date: July 14, 2016
    Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
  • Publication number: 20160184926
    Abstract: An ablation system includes an ablation tool configured to generate an energy beam to ablate an energy-sensitive material formed on at least one embedded feature of a workpiece. The ablation tool selects an initial fluence and an initial pulse rate of the energy beam to ablate a first portion of the energy-sensitive layer. The ablation tool further reduces at least one of the initial fluence and the initial pulse rate of the energy beam to ablate a second remaining portion of the energy-sensitive layer such that the embedded feature is exposed without being damaged or deformed.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 30, 2016
    Inventors: Courtney T. Sheets, Matthew E. Souter, Brian M. Erwin, Bouwe W. Leenstra, Nicholas A. Polomoff, Christopher L. Tessler
  • Publication number: 20160074968
    Abstract: A laser etching system includes a laser source configured to generate a plurality of laser pulses during an etching pass. A workpiece is aligned with respect to the laser source. The workpiece includes an etching material that is etched in response to receiving the plurality of laser pulses. A mask reticle is interposed between the laser source and the workpiece. The mask reticle includes at least one mask pattern configured to regulate the fluence or a number of laser pulses realized by the workpiece such that a plurality of features having different depths with respect to one another are etched in the etching material.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 17, 2016
    Inventors: Matthew E. Souter, Brian M. Erwin, Nicholas A. Polomoff, Christopher L. Tessler
  • Publication number: 20150357235
    Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.
    Type: Application
    Filed: August 18, 2015
    Publication date: December 10, 2015
    Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
  • Publication number: 20150348831
    Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicants: International Business Machines Corporation, SUSS MicroTec Photonic Systems Inc.
    Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
  • Patent number: 9132511
    Abstract: Various techniques are disclosed for an apparatus and a method to remove a layer from a substrate having a pattern formed on the layer. In one example, the apparatus comprises a stage configured to receive and hold the substrate. The apparatus may further comprise an irradiating device comprising a projection lens and configured to irradiate the surface of the substrate with pulses of laser light having a selected fluence to remove an interstitial portion of the layer between the pattern without removing the pattern for corresponding irradiated areas of the substrate. The pulses of laser light may be focused through the projection lens, and the stage and the projection lens may be configured to move continuously relative each other to irradiate a plurality of areas of the substrate with the pulses of laser light.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: September 15, 2015
    Assignee: SUSS MICROTEC PHOTONIC SYSTEMS, INC.
    Inventor: Matthew E. Souter
  • Publication number: 20150014287
    Abstract: Various techniques are disclosed for an apparatus and a method to remove a layer from a substrate having a pattern formed on the layer. In one example, the apparatus comprises a stage configured to receive and hold the substrate. The apparatus may further comprise an irradiating device comprising a projection lens and configured to irradiate the surface of the substrate with pulses of laser light having a selected fluence to remove an interstitial portion of the layer between the pattern without removing the pattern for corresponding irradiated areas of the substrate. The pulses of laser light may be focused through the projection lens, and the stage and the projection lens may be configured to move continuously relative each other to irradiate a plurality of areas of the substrate with the pulses of laser light.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 15, 2015
    Inventor: Matthew E. Souter
  • Patent number: 8778799
    Abstract: A method for making conductive traces and interconnects on a surface of a substrate includes, for an embodiment, forming a dielectric or polymer layer on the surface of the substrate, forming a seed layer of an electrically conductive material on the dielectric or polymer layer, patterning a photoresist on the seed layer, forming the conductive traces on the patterned photoresist and seed layer, removing the photoresist from the substrate, and irradiating the surface of the substrate with a fluence of laser light effective to ablate the seed layer from areas of the substrate surface exclusive of the conductive traces.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: July 15, 2014
    Assignee: Tamarack Scientific Co. Inc.
    Inventor: Matthew E. Souter
  • Publication number: 20120184099
    Abstract: A method for making conductive traces and interconnects on a surface of a substrate includes, for an embodiment, forming a dielectric or polymer layer on the surface of the substrate, forming a seed layer of an electrically conductive material on the dielectric or polymer layer, patterning a photoresist on the seed layer, forming the conductive traces on the patterned photoresist and seed layer, removing the photoresist from the substrate, and irradiating the surface of the substrate with a fluence of laser light effective to ablate the seed layer from areas of the substrate surface exclusive of the conductive traces.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 19, 2012
    Applicant: Tamarack Scientific Co. Inc.
    Inventor: Matthew E. Souter