Abstract: An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

Abstract: A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.

Abstract: An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the substrate and at least two conducting metal vias that are orthogonal to the substrate. A method of producing the self aligned vias by depositing an interlayer dielectric layer onto a substrate, depositing at least one hardmask onto the interlayer dielectric layer, lithographically forming a via pattern with elongated via features and lithographically forming a line pattern in either order, then either transferring the line patterns first into the interlayer dielectric layer forming line features or transferring the via pattern first into the interlayer dielectric layer as long as the patterns overlap to forming self aligned via features, depositing conducting metals and filling regions corresponding to the line and via features, and planarizing and removing excess metal from the line and via features.

Abstract: A method of forming a dual-damascene wire. The method includes forming a via opening in a dielectric layer, filling the via opening with a polymeric formation including at least about 6% by weight of solids of thermal acid generator; heating the polymeric underlayer to a temperature greater than room temperature but less than about 180° C.; lithographically forming a trench in the dielectric layer and filling the via opening and the trench with an electrical conductor, a top surface of the electrical conductor substantially co-planer with the top surface of the second dielectric capping layer.

Abstract: An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

Abstract: A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.

Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

Abstract: A method of forming a relief image in a structure comprising a substrate and a transfer layer formed thereon comprises covering the transfer layer with a polymerizable fluid composition, and then contacting the polymerizable fluid composition with a mold having a relief structure formed therein such that the polymerizable fluid composition fills the relief structure in the mold. The polymerizable fluid composition is subjected to conditions to polymerize polymerizable fluid composition and form a solidified polymeric material therefrom on the transfer layer. The mold is then separated from the solid polymeric material such that a replica of the relief structure in the mold is formed in the solidified polymeric material; and the transfer layer and the solidified polymeric material are subjected to an environment to selectively etch the transfer layer relative to the solidified polymeric material such that a relief image is formed in the transfer layer.

Abstract: A method of forming a relief image in a structure comprising a substrate and a transfer layer formed thereon comprises covering the transfer layer with a polymerizable fluid composition, and then contacting the polymerizable fluid composition with a mold having a relief structure formed therein such that the polymerizable fluid composition fills the relief structure in the mold. The polymerizable fluid composition is subjected to conditions to polymerize polymerizable fluid composition and form a solidified polymeric material therefrom on the transfer layer. The mold is then separated from the solid polymeric material such that a replica of the relief structure in the mold is formed in the solidified polymeric material; and the transfer layer and the solidified polymeric material are subjected to an environment to selectively etch the transfer layer relative to the solidified polymeric material such that a relief image is formed in the transfer layer.

Abstract: A method of forming a relief image in a structure comprising a substrate and a transfer layer formed thereon comprises covering the transfer layer with a polymerizable fluid composition, and then contacting the polymerizable fluid composition with a mold having a relief structure formed therein such that the polymerizable fluid composition fills the relief structure in the mold. The polymerizable fluid composition is subjected to conditions to polymerize polymerizable fluid composition and form a solidified polymeric material therefrom on the transfer layer. The mold is then separated from the solid polymeric material such that a replica of the relief structure in the mold is formed in the solidified polymeric material; and the transfer layer and the solidified polymeric material are subjected to an environment to selectively etch the transfer layer relative to the solidified polymeric material such that a relief image is formed in the transfer layer.