Patents by Inventor Matthew Edward King
Matthew Edward King has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8611368Abstract: Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.Type: GrantFiled: June 17, 2011Date of Patent: December 17, 2013Assignees: International Business Machines Corporation, Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Charles Ray Johns, Matthew Edward King, Peichun Peter Liu, David Mui, Jieming Qi
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Patent number: 8483227Abstract: Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.Type: GrantFiled: November 20, 2003Date of Patent: July 9, 2013Assignees: International Business Machines Corporation, Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Charles Ray Johns, Matthew Edward King, Peichun Peter Liu, David Mui, Jieming Qi
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Publication number: 20110246695Abstract: Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.Type: ApplicationFiled: June 17, 2011Publication date: October 6, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC., KABUSHIKI KAISHA TOSHIBAInventors: Shigehiro Asano, Charles Ray Johns, Matthew Edward King, Peichun Peter Liu, David Mui, Jieming Qi
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Patent number: 7895029Abstract: A system and method for modifying a simulation model and optimizing an application program to produce valid hardware-identified operating conditions that are matched with simulator-identified operating conditions in order to modify a simulator accordingly is presented. A critical path coverage analyzer includes critical path measurement logic into a simulation model that injects errors into the critical path and provides visibility into the number of times that an application program exercises the critical path. The critical path coverage analyzer uses the critical path measurement logic to optimize an application program to adequately exercise and test the critical paths. Once optimized, the critical path coverage analyzer runs the optimized application program on a hardware device to produce hardware-identified operating conditions. The hardware-identified operating conditions are matched against simulator-identified operating conditions.Type: GrantFiled: October 30, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Matthew Edward King, Charles Leverett Meissner, Todd Swanson, Michael Ellett Weissinger
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Patent number: 7877523Abstract: An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.Type: GrantFiled: December 10, 2008Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Matthew Edward King, Peichum Peter Liu, David Mui, Takeshi Yamazaki
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Patent number: 7644198Abstract: An improved DMAC translation mechanism is presented. DMA commands are “unrolled” based upon the transfer size of the DMA command and the amount of data that a computer system transfers at one time. For the first DMA request, a DMA queue requests a memory management unit to perform an address translation. The DMA queue receives a real page number from the MMU and, on subsequent rollout requests, the DMA queue provides the real page number to a bus interface unit without accessing the MMU until the transfer crosses into the next page. Rollout logic decrements the DMA command's transfer size after each DMA request, determines whether a new page has been reached, determines if the DMA command is completed, and sends write back information to the DMA queue for subsequent DMA requests.Type: GrantFiled: October 7, 2005Date of Patent: January 5, 2010Assignee: International Business Machines CorporationInventors: Matthew Edward King, Peichun Peter Lui, David Mui, Jieming Qi
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Publication number: 20090112557Abstract: A system and method for modifying a simulation model and optimizing an application program to produce valid hardware-identified operating conditions that are matched with simulator-identified operating conditions in order to modify a simulator accordingly is presented. A critical path coverage analyzer includes critical path measurement logic into a simulation model that injects errors into the critical path and provides visibility into the number of times that an application program exercises the critical path. The critical path coverage analyzer uses the critical path measurement logic to optimize an application program to adequately exercise and test the critical paths. Once optimized, the critical path coverage analyzer runs the optimized application program on a hardware device to produce hardware-identified operating conditions. The hardware-identified operating conditions are matched against simulator-identified operating conditions.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventors: Matthew Edward King, Charles Leverett Meissner, Todd Swanson, Michael Ellett Weissinger
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Publication number: 20090094388Abstract: An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.Type: ApplicationFiled: December 10, 2008Publication date: April 9, 2009Inventors: Matthew Edward King, Peichum Peter Liu, David Mui, Takeshi Yamazaki
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Patent number: 7512722Abstract: A method, an apparatus, and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.Type: GrantFiled: July 31, 2003Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Matthew Edward King, Peichum Peter Liu, David Mui, Takeshi Yamazaki
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Patent number: 7444435Abstract: A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one processor has a local storage. The DMAC includes a DMA command queue (DMAQ) coupled to the local storage and configured to receive the list DMA command from the local storage and to enqueue the list DMA command. An issue logic is coupled to the DMAQ and configured to issue an issue request to the DMAQ. A request interface logic (RIL) is coupled to the DMAQ and configured to read the list DMA command based on the issue request. The RIL is further coupled to the local storage and configured to send a fetch request to the local storage to initiate a fetch of a list element of the list DMA command from the local storage to the DMAQ.Type: GrantFiled: March 14, 2007Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: Matthew Edward King, Peichum Peter Liu, David Mui, Takeshi Yamazaki
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Publication number: 20070083680Abstract: A system and method for improved DMAC translation mechanism is presented. DMA commands are “unrolled” based upon the transfer size of the DMA command and the amount of data that a computer system transfers at one time. For the first DMA request, a DMA queue requests a memory management unit to perform an address translation. The DMA queue receives a real page number from the MMU and, on subsequent rollout requests, the DMA queue provides the real page number to a bus interface unit without accessing the MMU until the transfer crosses into the next page. Rollout logic decrements the DMA command's transfer size after each DMA request, determines whether a new page has been reached, determines if the DMA command is completed, and sends write back information to the DMA queue for subsequent DMA requests.Type: ApplicationFiled: October 7, 2005Publication date: April 12, 2007Inventors: Matthew Edward King, Peichun Peter Lui, David Mui, Jieming Qi
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Patent number: 7203811Abstract: A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.Type: GrantFiled: July 31, 2003Date of Patent: April 10, 2007Assignee: International Business Machines CorporationInventors: Matthew Edward King, Peichum Peter Liu, David Mui, Takeshi Yamazaki
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Patent number: 6738070Abstract: A method and an apparatus for retrieving a mipmap from memory. The method and apparatus provide an efficient method of determining the location of the desired mipmap in memory by storing the address of each row of mipmaps and calculating the offset from the start of the row to the desired mipmap. The mipmap is retrieved from memory at the location corresponding to the sum of the start address and the offset.Type: GrantFiled: January 7, 2002Date of Patent: May 18, 2004Assignee: International Business Machines CorporationInventors: Daniel Alan Brokenshire, David Arthur Dick, Matthew Edward King, William B. Tiernan
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Publication number: 20030128217Abstract: A method and an apparatus for retrieving a mipmap from memory. The method and apparatus provide an efficient method of determining the location of the desired mipmap in memory by storing the address of each row of mipmaps and calculating the offset from the start of the row to the desired mipmap. The mipmap is retrieved from memory at the location corresponding to the sum of the start address and the offset.Type: ApplicationFiled: January 7, 2002Publication date: July 10, 2003Applicant: International Business Machines CorporationInventors: Daniel Alan Brokenshire, David Arthur Dick, Matthew Edward King, William B. Tiernan