Patents by Inventor Matthew Escobido

Matthew Escobido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • C4 joint reliability
    Patent number: 7656035
    Abstract: In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventors: Sairam Agraharam, Carlton Hanna, Dongming He, Vasudeva Atluri, Debendra Mallik, Matthew Escobido, Sujit Sharan
  • C4 JOINT RELIABILITY
    Publication number: 20090115057
    Abstract: In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.
    Type: Application
    Filed: January 9, 2009
    Publication date: May 7, 2009
    Inventors: Sairam Agraharam, Carlton Hanna, Dongming He, Vasudeva Atluri, Debendra Mallik, Matthew Escobido, Sujit Sharan
  • C4 joint reliability
    Patent number: 7517787
    Abstract: In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Sairam Agraharam, Carlton Hanna, Dongming He, Vasudeva Atluri, Debendra Mallik, Matthew Escobido, Sujit Sharan
  • C4 joint reliability
    Publication number: 20060214292
    Abstract: In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.
    Type: Application
    Filed: March 22, 2005
    Publication date: September 28, 2006
    Inventors: Sairam Agraharam, Carlton Hanna, Dongming He, Vasudeva Atluri, Debendra Mallik, Matthew Escobido, Sujit Sharan