Abstract: A banking pipeline for processing various transactions for multiple financial instruments is disclosed herein. The pipeline may have three distinct interpreters, a transaction interpreter, a rollup interpreter, and a rules interpreter. Different aspects of the transaction may be performed on separate interpreters and each interpreter may perform its aspect of the transaction before the next interpreter begins.

Abstract: Instruction decoder circuitry decodes processing instructions each generating an output multi-bit data item in a destination architectural register by applying a processing operation to source data item(s) in respective source architectural register(s). The decoder circuitry detects whether an instruction defines a predicated merge operation that propagates a set of zero or more portions of the prevailing contents of the destination architectural register as respective portions of the output multi-bit data item. The portions are defined by predicate data. Register allocation circuitry associates physical registers with the destination architectural register and the source architectural register(s). When detector circuitry detects that an instruction defines a predicated merge operation, the register allocation circuitry associates a further physical register with that instruction to store a copy of the prevailing contents.

Abstract: Instruction decoder circuitry decodes processing instructions each generating an output multi-bit data item in a destination architectural register by applying a processing operation to source data item(s) in respective source architectural register(s). The decoder circuitry detects whether an instruction defines a predicated merge operation that propagates a set of zero or more portions of the prevailing contents of the destination architectural register as respective portions of the output multi-bit data item. The portions are defined by predicate data. Register allocation circuitry associates physical registers with the destination architectural register and the source architectural register(s). When detector circuitry detects that an instruction defines a predicated merge operation, the register allocation circuitry associates a further physical register with that instruction to store a copy of the prevailing contents.

Abstract: A banking pipeline for processing various transactions for multiple financial instruments is disclosed herein. The pipeline may have three distinct interpreters, a transaction interpreter, a rollup interpreter, and a rules interpreter. Different aspects of the transaction may be performed on separate interpreters and each interpreter may perform its aspect of the transaction before the next interpreter begins.

Abstract: A system using neurological control signals to control a device is disclosed. The system may include a sensor sensing electrical activity of a plurality of neurons over time and a vector generator generating a neural control vector from the sensed electrical activity of the plurality of neurons over time. The system may also include a control filter to which the neural control vector is applied to provide a control variable and an output device controlled by the control variable.