Patents by Inventor Matthew Fisch

Matthew Fisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6009477
    Abstract: Each of a plurality of device or agents connected to a computer system bus is provided with a mechanism for unilaterally and dynamically limiting the depth of a pipeline of the bus. Each agent includes a state machine which indicates whether the bus is in a throttled state, a stalled state or a free state. When in a free state, an agent having control of the bus may transmit any number of bus transactions and the depth of the pipeline may therefore increase. In the throttled state, the agent may transmit only a single bus transaction from the throttled state, the state machine always transitions either to the stalled state or to the free state. In the stalled state, no agents may transmit transactions onto the bus and the depth of the pipeline therefore cannot increase and instead may decrease with time as previously issued transactions are drained from the bus.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: December 28, 1999
    Assignee: Intel Corporation
    Inventors: Nitin Sarangdhar, Michael Rhodehamel, Matthew Fisch
  • Patent number: 5948088
    Abstract: Each of a plurality of device or agents connected to a computer system bus is provided with a mechanism for unilaterally and dynamically limiting the depth of a pipeline of the bus. Each agent includes a state machine which indicates whether the bus is in a throttled state, a stalled state or a free state. When in a free state, an agent having control of the bus may transmit any number of bus transactions and the depth of the pipeline may therefore increase. In the throttled state, the agent may transmit only a single bus transaction from the throttled state, the state machine always transitions either to the stalled state or to the free state. In the stalled state, no agents may transmit transactions onto the bus and the depth of the pipeline therefore cannot increase and instead may decrease with time as previously issued transactions are drained from the bus.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: September 7, 1999
    Assignee: Intel Corporation
    Inventors: Nitin Sarangdhar, Michael Rhodehamel, Matthew Fisch
  • Patent number: 5761449
    Abstract: A bus system for a computer having multiple agents provides a mechanism for unilaterally and dynamically limiting the pipelining depth. Each agent includes a state machine which indicates whether the bus is in a throttled state, a stalled state or a free state. When in a free state, an agent having control of the bus may transmit any number of bus transactions and the depth of the pipeline may therefore increase. In the throttled state, the agent may transmit only a single bus transaction from the throttled state. The state machine always transitions either to the stalled state or to the free state. In the stalled state, no agents may transmit transactions onto the bus and the depth of the pipeline therefore cannot increase and instead may decrease with time as previously issued transactions are drained from the bus.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: June 2, 1998
    Assignee: Intel Corporation
    Inventors: Nitin Sarangdhar, Michael Rhodehamel, Matthew Fisch
  • Patent number: 5572703
    Abstract: A protocol and related apparatus for snoop stretching in a computer system having at least one requesting agent for issuing bus transaction requests and at least one snooping agent for monitoring transaction requests and issuing bus signals onto an external bus. The bus transactions are timed by a bus clock signal having a plurality of cycles. To indicate snoop stretching, during a first cycle a first snooping agent asserts both a HIT# bus signal and a HITM# bus signal together to indicate that the first snooping agent must delay assertion of valid snoop results for a predetermined snoop period. During a later cycle, to indicate the end of the snoop stretch, the first snooping agent deasserts the assertion of both the HIT# and HITM# signals together and asserts its valid snoop results. The HIT# and HITM# signals alone each represent valid snoop results.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: November 5, 1996
    Assignee: Intel Corporation
    Inventors: Peter MacWilliams, Nitin V. Sarangdhar, Matthew Fisch, Amit Merchant
  • Patent number: 5551005
    Abstract: In a computer system having a plurality of processors with internal caches, a method for handling race conditions arising when multiple processors simultaneously write to a particular cache line. Initially, a determination is made as to whether the cache line is in an exclusive, modified, invalid, or shared state. If the cache line is in either the exclusive or modified state, the cache line is written to and then set to the modified state. If the cache line is in the invalid state, a Bus-Read-Invalidate operation is performed. However, if the cache line is in the shared state and multiple processors initiate Bus-Write-Invalidate operations, the invalidation request belonging to the first processor is allowed to complete. Thereupon, the cache line is sent to the exclusive state, data is updated, and the cache line is set to the modified state. The second processor receives a second cache line, updates this second cache line, and sets the second cache line to the modified state.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: August 27, 1996
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Wen-Hann Wang, Matthew Fisch
  • Patent number: 5548733
    Abstract: Each of a plurality of devices or agents connected to a computer system bus is provided with a mechanism for unilaterally and dynamically limiting the depth of a pipeline of the bus. Each agent includes a state machine which indicates whether the bus is in a throttled state, a stalled state or a free state. When in a free state, an agent having control of the bus may transmit any number of bus transactions and the depth of the pipeline may therefore increase. In the throttled state, the agent may transmit only a single bus transaction from the throttled state. The state machine always transitions either to the stalled state or to the free state. In the stalled state, no agents may transmit transactions onto the bus and the depth of the pipeline therefore cannot increase and instead may decrease with time as previously issued transactions are drained from the bus.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: August 20, 1996
    Assignee: Intel Corporation
    Inventors: Nitin Sarangdhar, Michael Rhodehamel, Matthew Fisch