Patents by Inventor Matthew Flaugh

Matthew Flaugh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12272558
    Abstract: Selective protection and etching is provided which can be utilized in etching of a silicon containing layer with respect to a Ge or SiGe layer. In an example, the layers are stacked, and an oxide is on a side surface of the layers. A treatment is utilized to provide a modified surface or termination surface on side surfaces of the Ge/SiGe layers, and a heat treatment is provided after the gas treatment to selectively sublimate layer portions on side surfaces of the Si containing layers. The gas treatment and heat treatment are preferably in non-plasma environments. Thereafter, a plasma process is performed to form a protective layer on the Ge containing layers, and the Si containing layers can be etched with the plasma.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: April 8, 2025
    Assignee: Tokyo Electron Limited
    Inventors: Matthew Flaugh, Jonathan Hollin, Subhadeep Kal, Pingshan Luan, Hamed Hajibabaeinajafabadi, Yu-Hao Tsai, Aelan Mosden
  • Publication number: 20240096639
    Abstract: A surface of a substrate is modified, where the substrate includes at least two different layers or films of different materials. The modified layer is then selectively converted to a protection layer on one of the layers, while the other layer is etched.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jonathan HOLLIN, Matthew Flaugh, Subhadeep Kal, Aelan Mosden
  • Publication number: 20230360921
    Abstract: Selective protection and etching is provided which can be utilized in etching of a silicon containing layer with respect to a Ge or SiGe layer. In an example, the layers are stacked, and an oxide is on a side surface of the layers. A treatment is utilized to provide a modified surface or termination surface on side surfaces of the Ge/SiGe layers, and a heat treatment is provided after the gas treatment to selectively sublimate layer portions on side surfaces of the Si containing layers. The gas treatment and heat treatment are preferably in non-plasma environments. Thereafter, a plasma process is performed to form a protective layer on the Ge containing layers, and the Si containing layers can be etched with the plasma.
    Type: Application
    Filed: October 12, 2022
    Publication date: November 9, 2023
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Matthew FLAUGH, Jonathan HOLLIN, Subhadeep KAL, Pingshan LUAN, Hamed HAJIBABAEINAJAFABADI, Yu-Hao TSAI, Aelan MOSDEN
  • Patent number: 11715643
    Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 1, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Subhadeep Kal, Daisuke Ito, Matthew Flaugh, Yusuke Muraki, Aelan Mosden
  • Patent number: 11189499
    Abstract: Methods for the atomic layer etch (ALE) of tungsten or other metal layers are disclosed that use in part sequential oxidation and reduction of tungsten/metal layers to achieve target etch parameters. For one embodiment, a metal layer is first oxidized to form a metal oxide layer and an underlying metal layer. The metal oxide layer is then reduced to form a surface metal layer and an underlying metal oxide layer. The surface metal layer is then removed to leave the underlying metal oxide layer and the underlying metal layer. Further, the oxidizing, reducing, and removing processes can be repeated to achieve a target etch depth. In addition, a target etch rate can also achieved for each process cycle of oxidizing, reducing, and removing.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yu-Hao Tsai, Du Zhang, Mingmei Wang, Aelan Mosden, Matthew Flaugh
  • Publication number: 20210020454
    Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.
    Type: Application
    Filed: June 2, 2020
    Publication date: January 21, 2021
    Inventors: Subhadeep Kal, Daisuke Ito, Matthew Flaugh, Yusuke Muraki, Aelan Mosden
  • Publication number: 20200312673
    Abstract: Methods for the atomic layer etch (ALE) of tungsten or other metal layers are disclosed that use in part sequential oxidation and reduction of tungsten/metal layers to achieve target etch parameters. For one embodiment, a metal layer is first oxidized to form a metal oxide layer and an underlying metal layer. The metal oxide layer is then reduced to form a surface metal layer and an underlying metal oxide layer. The surface metal layer is then removed to leave the underlying metal oxide layer and the underlying metal layer. Further, the oxidizing, reducing, and removing processes can be repeated to achieve a target etch depth. In addition, a target etch rate can also achieved for each process cycle of oxidizing, reducing, and removing.
    Type: Application
    Filed: February 27, 2020
    Publication date: October 1, 2020
    Inventors: Yu-Hao Tsai, Du Zhang, Mingmei Wang, Aelan Mosden, Matthew Flaugh