Patents by Inventor Matthew Fortune

Matthew Fortune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250130806
    Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 24, 2025
    Inventors: James Hippisley Robinson, Morgyn Taylor, Matthew Fortune, Richard Fuhler, Sanjay Patel
  • Patent number: 12210876
    Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 28, 2025
    Assignee: MIPS Tech, LLC
    Inventors: James Hippisley Robinson, Morgyn Taylor, Matthew Fortune, Richard Fuhler, Sanjay Patel
  • Publication number: 20240411587
    Abstract: Disclosed herein is a graph streaming processing system comprising a thread scheduler comprising a first component and a second component. The first component is configured to schedule a first set of threads of a first node to a first processor associated with the first node and initialize status of a completion pointer to an initial value. The completion pointer is associated with a command buffer of the first node. The first component is configured to detect the execution of the first set of threads and generation of a data unit and update the status of the completion pointer to an updated value indicating execution of the first set of threads in response to the generation of the data unit. The second component is configured to schedule a second set of threads of a plurality of second nodes to a second processor based on the status of the completion pointer.
    Type: Application
    Filed: July 1, 2023
    Publication date: December 12, 2024
    Applicant: Blaize, Inc.
    Inventors: Venkata Ganapathi Puppala, Kota Vamsi Darsi, Matthew Fortune
  • Publication number: 20190065201
    Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.
    Type: Application
    Filed: August 31, 2018
    Publication date: February 28, 2019
    Inventors: James Hippisley Robinson, Morgyn Taylor, Matthew Fortune, Richard Fuhler, Sanjay Patel
  • Publication number: 20190065199
    Abstract: Described herein are instruction set architectures (ISAs), and related data processing apparatuses and methods, with two or more non-contiguous blocks of preserved registers wherein the registers to be saved or restored are identified in a save or restore instruction via a number of registers to be saved/restored (Num_Reg) and a starting register (rStart). Specifically, in the ISAs, apparatuses, and methods described herein, the registers to be saved or restored are identified as the Num_Reg registers in a predetermined sequence starting with rStart wherein, in the predetermined sequence, each register is followed by the next highest numbered register except the highest numbered preserved register, which is followed by the lowest numbered preserved register.
    Type: Application
    Filed: August 31, 2018
    Publication date: February 28, 2019
    Inventors: James Hippisley Robinson, Morgyn Taylor, Matthew Fortune