Patents by Inventor Matthew Francis Seward

Matthew Francis Seward has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6721187
    Abstract: A multi-layer electronic structure includes an increased capacity for the attachment of active or passive devices thereto. This is achieved by creating a three-dimensional grid of connection points to electrically couple active or passive surface mounted devices to edge mounted devices. The grid pattern is useful with any laminate including circuit cards, ceramic modules and flexible circuits. The variety of electrical devices that may be connected to the cross-sectional substrate includes, but is not limited to, chips such as semiconductor chips, diodes, resistors, capacitors and printed wiring boards. The structure can be used to more rapidly pass data, such as optical data that is transmitted from a spectroscope through a VCSEL laser and the electronic structure to a computer for diagnostics and analysis. A stepped arrangement of circuitized laminates is described for this purpose.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: April 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Richard Ronald Hall, How Tzu Lin, Christopher John Majka, Norman Corey Seastrand, Matthew Francis Seward, Ronald Verne Smith
  • Patent number: 6651013
    Abstract: A method and apparatus for locating a short between two nets in an electrical wire network of a microelectronic structure (e.g., chip, chip carrier, circuit card, etc.). A first net and a second net of the electrical wire are electrically shorted at an unknown point PS on the first net. Points PA and PB on the first net such are selected such that PS is located on a path between PA and PB along the first net. A constant current pulse source is electrically connected between PA and PB and is activated. Voltage drops VAB (from PA to PB) and VAC (from PA to a point PC on the second net) are measured. A length LAS of the path from PA to PS is calculated as a function of VAC/VAB. Computer graphics may be used to graphically display the location of the short within the microelectronic structure.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: How T. Lin, Christopher J. Majka, Matthew Francis Seward
  • Publication number: 20020131252
    Abstract: A multi-layer electronic structure includes an increased capacity for the attachment of active or passive devices thereto. This is achieved by creating a three-dimensional grid of connection points to electrically couple active or passive surface mounted devices to edge mounted devices. The grid pattern is useful with any laminate including circuit cards, ceramic modules and flexible circuits. The variety of electrical devices that may be connected to the cross-sectional substrate includes, but is not limited to, chips such as semiconductor chips, diodes, resistors, capacitors and printed wiring boards. The structure can be used to more rapidly pass data, such as optical data that is transmitted from a spectroscope through a VCSEL laser and the electronic structure to a computer for diagnostics and analysis. A stepped arrangement of circuitized laminates is described for this purpose.
    Type: Application
    Filed: March 16, 2001
    Publication date: September 19, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard Ronald Hall, How Tzu Lin, Christopher John Majka, Norman Corey Seastrand, Matthew Francis Seward, Ronald Verne Smith