Abstract: The multiple stream traffic emulator functions to generate multiple stream packet based traffic pursuant to a selected statistical model. The generation of the traffic is controlled by an element that generates data indicative of a pattern of data traffic for each of a plurality of input data streams. This element can either produce this data in real time or this data can be resident in memory. In the real time application, a processor, such as a digital signal processor (DSP), can be used to generate the data. In the pregenerated data instance, the data is typically produced by an external processing element and stored in a memory, where either the user can select from among various types of data stored in the memory, or the data for use in a single traffic emulation instance is stored in the memory. In one implementation of the system, an interdeparture queue is used to store data representative of a selected statistical traffic model, comprising both a pattern of data traffic and a traffic load.

Abstract: A justifier for parallel justifying data onto a DS-3 mapping includes an input bus for selectively communicating 8 respective I bits simultaneously to the justifier. An output bus receives I, R, O and C bits from the justifier in accordance with the mapping at an eighth of the envelope rate of 44.736 Mb/s. A first data path connected to an input bus via a latch communicates a required number of the I bits to the output bus, during a first cycle of GCLK. A second data path connected to the input bus via the same latch communicates the remainder of the I bits to the output bus over one or more subsequent GCLK cycles to satisfy the mapping. The justifier includes a controller for regulating the flow of the I bits along first and second paths. The controller responds to a first control indicative of the mapping to be followed as provided by a sequencer.