Patents by Inventor Matthew G Borlick

Matthew G Borlick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11663144
    Abstract: A method for improving cache hit ratios for selected storage elements within a storage system includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. The favored storage elements are retained in the cache longer than the non-favored storage elements. The method maintains a first LRU list containing entries associated with non-favored storage elements and designating an order in which the non-favored storage elements are evicted from the cache, and a second LRU list containing entries associated with favored storage elements and designating an order in which the favored storage elements are evicted from the cache. The method periodically scans the first LRU list for non-favored storage elements that have changed to favored storage elements, and the second LRU list for favored storage elements that have changed to non-favored storage elements. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Matthew G. Borlick, Beth A. Peterson
  • Patent number: 11663129
    Abstract: Provided are a computer program product, system, and method for determining tracks to prestage into cache from a storage. Information is provided related to determining tracks to prestage from the storage to the cache in a stage group of sequential tracks including a trigger track comprising a track number in the stage group at which to start prestaging tracks and Input/Output (I/O) activity information to a machine learning module. A new trigger track in the stage group at which to start prestaging tracks is received from the machine learning module having processed the provided information. The trigger track is set to the new trigger track. Tracks are prestaged in response to processing an access request to the trigger track in the stage group.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: May 30, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11651070
    Abstract: Provided are a computer program product, system, and method for detecting a security breach in a system managing access to a storage. Process Input/Output (I/O) activity by a process accessing data in a storage is monitored. A determination is made of a characteristic of the data subject to the I/O activity from the process. A determination is made as to whether a characteristic of the process I/O activity as compared to the characteristic of the data satisfies a condition. The process initiating the I/O activity is characterized as a suspicious process in response to determining that the condition is satisfied. A security breach is indicated in response to characterizing the process as the suspicious process.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: May 16, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11641349
    Abstract: Aspects of the present disclosure relate to encryption management. A determination can be made whether an encryption algorithm is at-risk. In response to determining that the encryption algorithm is at-risk, data protected by the encryption algorithm can be identified. A security action can then be executed on the data protected by the encryption algorithm.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: May 2, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Mark Elliott Hack, Micah Robison
  • Patent number: 11620218
    Abstract: A computer-implemented method, according to one approach, includes: determining whether to satisfy an I/O request using a first tier of memory in a secondary cache by inspecting a bypass indication in response to determining that the input/output (I/O) request includes a bypass indication. The secondary cache is coupled to a primary cache and a data storage device. The secondary cache also includes the first tier of memory and a second tier of memory. Moreover, in response to determining to satisfy the I/O request using the first tier of memory in the secondary cache, the I/O request is satisfied using the first tier of memory in the secondary cache. The updated data is also destaged from the secondary cache to the data storage device in response to determining that data associated with the I/O request has been updated as the result of satisfying the I/O request using the secondary cache.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: April 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Edward Hsiu-Wei Lin, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11620219
    Abstract: In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 11620226
    Abstract: A method to prevent starvation of non-favored volumes in cache is disclosed. In one embodiment, such a method includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. A cache demotion algorithm is used to retain the favored storage elements in the cache longer than the non-favored storage elements. The method designates a maximum amount of storage space that the favored storage elements are permitted to consume in the cache. In preparation to free storage space in the cache, the method determines whether an amount of storage space consumed by the favored storage elements in the cache has reached the maximum amount. If so, the method frees storage space in the cache by demoting favored storage elements. If not, the method frees storage space in the cache in accordance with the cache demotion algorithm. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 9, 2020
    Date of Patent: April 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Matthew G. Borlick, Beth A. Peterson
  • Patent number: 11620055
    Abstract: Provided are computer program product, system, and method for managing data structures in a plurality of memory devices that are indicated to demote after initialization of the data structures. Indication is made to data structures to demote after initialization from a first level memory device to a second level memory device. The first level memory device has lower latency than the second level memory device. In response to completing initialization of the data structures in the first level memory device, the data structures indicated to demote after initialization are copied from the first level memory device to the second level memory device and removing the data structures indicate to move after initialization from the first level memory device.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: April 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew Richard Craig, Matthew G. Borlick
  • Publication number: 20230073544
    Abstract: Provided are a computer program product, system, and method for determining status of tracks in storage cached in a cache for a host. A storage controller receives from the host a list of tracks for the host to access and determines whether the tracks in the list are available in the cache for immediate access. A response is returned to the host indicating the tracks as one of available in the cache for immediate access and not available in the cache for immediate access.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 9, 2023
    Inventors: Lokesh Mohan Gupta, Beth Ann Peterson, Matthew G. Borlick, Matthew J. Kalos
  • Publication number: 20230070794
    Abstract: Provided are a computer program product, system, and method for using track status information on active or inactive status of track to determine whether to process a host request on a fast access channel. A host request to access a target track is received on a first channel to the host. A determination is made as to whether the target track has active or inactive status. The target track has active status when at least one process currently maintains a lock on the target track that prevents access and the target track has inactive status when no process maintains a lock on the target track that prevents access. Fail is returned to the host to cause the host to resend the host request on a second channel in response to the target track having the active status. The first channel has lower latency than the second channel.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 9, 2023
    Inventors: Lokesh Mohan Gupta, Beth Ann Peterson, Matthew G. Borlick
  • Publication number: 20230075922
    Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 9, 2023
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11580022
    Abstract: In one aspect of write sort management in accordance with the present disclosure, a sort/no-sort determination is made prior to issuing to a write command to a target storage controller. The write command identifies a write data unit such track write data, for example, of a first write list of write data units to be written to storage locations of storage. The write command further identifies the storage location at which the write data unit of the first write list is to be stored. In one embodiment, the sort/no-sort determination determines whether an insertion point for an entry in a target write list is to be determined as a function of a write list search such as a logarithmic time search for a write list sort. As a result, the write list search for a write list sort, may be selectively either performed or bypassed for insertion of the target write list entry as a function of the sort/no-sort determination Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: February 14, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian D. Hatfield, Lokesh Mohan Gupta, Matthew G. Borlick
  • Patent number: 11573709
    Abstract: Provided are a computer program product, system, and method for maintaining data structures in a virtual memory comprised of a plurality of heterogeneous memory devices. Access counts are maintained for a plurality of data structures stored in a first level memory device. A determination is made of data structures in the first level memory device having lowest access counts. The determined data structures are deleted from the first level memory device and retaining copies of the data structures in a second level memory device, wherein the first level memory device has lower latency than the second level memory device.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: February 7, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew Richard Craig, Matthew G. Borlick
  • Publication number: 20230036755
    Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 2, 2023
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11561905
    Abstract: A minimum retention time in cache is indicated for a first plurality of tracks, where no minimum retention time is indicated for a second plurality of tracks. A cache management application demotes a track of the first plurality of tracks from the cache, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the cache and the track has been in the cache for a time that exceeds the minimum retention time.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: January 24, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Joseph Hayward, Matthew G. Borlick
  • Patent number: 11550726
    Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 10, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11550732
    Abstract: A method for maintaining statistics for data elements in a cache is disclosed. The method maintains a heterogeneous cache comprising a higher performance portion and a lower performance portion. The method maintains, within the lower performance portion, a ghost cache containing statistics for data elements that are currently contained in the heterogeneous cache, and data elements that have been demoted from the heterogeneous cache within a specified time interval. The method calculates a size of the ghost cache based on an amount of frequently accessed data that is stored in backend storage volumes behind the heterogeneous cache. The method alters the size of the ghost cache as the amount of frequently accessed data changes. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 22, 2020
    Date of Patent: January 10, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Patent number: 11520631
    Abstract: A plurality of processing entities in which a plurality of tasks are executed are maintained. Memory access patterns are determined for each of the plurality of tasks by dividing a memory associated with the plurality of processing entities into a plurality of memory regions, and for each of the plurality of tasks, determining how many memory accesses take place in each of the memory regions, by incrementing a counter associated with each memory region in response to a memory access. Each of the plurality of tasks are allocated among the plurality of processing entities, based on the determined memory access patterns for each of the plurality of tasks.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 11520515
    Abstract: A computational device generates a point in time copy of one or more regions of a time locked data set, in response to receiving one or more I/O operations directed to the time locked data set. The one or more I/O operations are performed on the point in time copy of the one or more regions of the time locked data set, in response to generating the point in time copy of the one or more regions of the time locked data set.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11461242
    Abstract: A computational device receives indications of a minimum retention time and a maximum retention time in cache for a first plurality of tracks, wherein no indications of a minimum retention time or a maximum retention time in the cache are received for a second plurality of tracks. A cache management application demotes a track of the first plurality of tracks from the cache, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the cache and the track has been in the cache for a time that exceeds the minimum retention time. The cache management application demotes the track of the first plurality of tracks, in response to determining that the track has been in the cache for a time that exceeds the maximum retention time.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: October 4, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Joseph Hayward, Kyler A. Anderson, Matthew G. Borlick