Abstract: A susceptor including a generally circular body having a face with a radially inward section and a radially outward section proximate a circumference of the body, the radially outward section having at least one ring extending upward for contacting a bottom surface of a substrate, and wherein the radially inward section lacks a ring extending upward from the face.

Abstract: A susceptor including a generally circular body having a face with a radially inward section and a radially outward section proximate a circumference of the body, the radially outward section having at least one ring extending upward for contacting a bottom surface of a substrate, and wherein the radially inward section lacks a ring extending upward from the face.

Abstract: A susceptor including a generally circular body having a face with a radially inward section and a radially outward section proximate a circumference of the body, the radially outward section having at least one ring extending upward for contacting a bottom surface of a substrate, and wherein the radially inward section lacks a ring extending upward from the face.

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Abstract: In some embodiments, a method for integrated circuit fabrication includes removing oxide material from a surface of a substrate, where the surface includes silicon and germanium. Removing the oxide material includes depositing a halogen-containing pre-clean material on a silicon oxide-containing surface and sublimating a portion of the halogen-containing pre-clean material to expose the silicon on the surface. A passivation film is deposited on the exposed silicon. The passivation film may include chlorine. The passivation film may prevent contamination of the silicon surface by chemical species from the later sublimation, which may be at a higher temperature than the earlier sublimation. Subsequently, a remaining portion of the halogen-containing pre-clean material and the passivation film are sublimated. A target material, such as a conductive material, may subsequently be deposited on the substrate surface.

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Abstract: In some embodiments, a method for integrated circuit fabrication includes removing oxide material from a surface of a substrate, where the surface includes silicon and germanium. Removing the oxide material includes depositing a halogen-containing pre-clean material on a silicon oxide-containing surface and sublimating a portion of the halogen-containing pre-clean material to expose the silicon on the surface. A passivation film is deposited on the exposed silicon. The passivation film may include chlorine. The passivation film may prevent contamination of the silicon surface by chemical species from the later sublimation, which may be at a higher temperature than the earlier sublimation. Subsequently, a remaining portion of the halogen-containing pre-clean material and the passivation film are sublimated. A target material, such as a conductive material, may subsequently be deposited on the substrate surface.

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Abstract: A method of forming a semiconductor material incorporating an electrical dopant is disclosed. In one aspect, a method of incorporating dopant in a semiconductor film comprises forming a first semiconductor material incorporating the dopant at a first dopant concentration and preferentially etching a portion of the first semiconductor material, wherein etching leaves a first etched semiconductor material incorporating the dopant at a second dopant concentration higher than the first dopant concentration.

Abstract: A method of forming a semiconductor material incorporating an electrical dopant is disclosed. In one aspect, a method of incorporating dopant in a semiconductor film comprises forming a first semiconductor material incorporating the dopant at a first dopant concentration and preferentially etching a portion of the first semiconductor material, wherein etching leaves a first etched semiconductor material incorporating the dopant at a second dopant concentration higher than the first dopant concentration.

Abstract: A susceptor including a generally circular body having a face with a radially inward section and a radially outward section proximate a circumference of the body, the radially outward section having at least one ring extending upward for contacting a bottom surface of a substrate, and wherein the radially inward section lacks a ring extending upward from the face.

Abstract: Methods and systems for calibrating a temperature control system in a vapor deposition chamber. A temperature sensor senses temperature within a semiconductor processing chamber and generates an output signal. A temperature control system controls a chamber temperature by controlling a heating apparatus based on the output signal. A method includes instructing the control system to target a setpoint temperature, and depositing a layer of material onto a surface in the chamber by a vapor deposition process. A variation of a property of the layer is measured while depositing the layer, the property known to vary cyclically as a thickness of the layer increases. The measured property is allowed to vary cyclically for one or more cycles. If there is a difference between a time period of one or more of the cycles and an expected time period associated with the setpoint temperature, the temperature control system is adjusted based on the difference.

Abstract: A substrate support system comprises a substrate holder for supporting a substrate. The substrate holder comprises an interior portion sized and shaped to extend beneath most or all of a substrate supported on the substrate holder. The substrate holder has mass density that varies, preferably in order to compensate for variations in substrate temperature owing to surface geometry variations of the interior portion, so as to provide a more uniform thermal coupling between the substrate and substrate holder. The substrate holder is preferably configured to be spaced further apart from a substrate at the center than at the outer perimeter.

Abstract: A substrate support system comprises a substrate holder for supporting a substrate. The substrate holder comprises a central portion sized and shaped to extend beneath most or all of a substrate supported on the substrate holder. The central portion has one or more recesses defining thinned portions of the central portion. The one or more thinned portions may comprise at least about 10% of an upper or lower surface of the central portion. The central portion is formed of a porous material, such as a material having a porosity between about 10-40%, configured to allow gas flow therethrough.

Abstract: Methods and systems for calibrating a temperature control system in a vapor deposition chamber. A temperature sensor senses temperature within a semiconductor processing chamber and generates an output signal. A temperature control system controls a chamber temperature by controlling a heating apparatus based on the output signal. A method includes instructing the control system to target a setpoint temperature, and depositing a layer of material onto a surface in the chamber by a vapor deposition process. A variation of a property of the layer is measured while depositing the layer, the property known to vary cyclically as a thickness of the layer increases. The measured property is allowed to vary cyclically for one or more cycles. If there is a difference between a time period of one or more of the cycles and an expected time period associated with the setpoint temperature, the temperature control system is adjusted based on the difference.

Abstract: A wafer holder for supporting a wafer within a CVD processing chamber includes a vertically moveable lift ring configured to support the bottom peripheral surface of the wafer, and an inner plug having a top flat surface configured to support the wafer during wafer processing. The lift ring has a central aperture configured to closely surround the inner plug. When a wafer is to be loaded onto the wafer holder, the lift ring is elevated above the inner plug. The wafer is loaded onto the lift ring in the elevated position. Then, the lift ring is maintained in the elevated position for a time period sufficient to allow the wafer temperature to rise to a level that is sufficient to significantly reduce or even substantially prevent thermal shock to the wafer when the wafer is brought into contact with the inner plug. The lift ring is then lowered into surrounding engagement with the inner plug. This is the wafer processing position of the wafer holder.

Abstract: A wafer holder comprises a circular, disc-shaped main portion and a rib extending generally downward from a lower surface of the main portion. The rib encircles the vertical center axis of the wafer holder. The upper surface of the main portion has a wafer-receiving pocket defined by an inner pocket surface surrounded by an outer shoulder. The rib is closed to completely surround a vertical center axis of the main portion. The rib helps to prevent the main portion from inducing symmetric concavity during the manufacture of the wafer holder. In other words, the rib helps to maintain the flatness of the upper surface of the outer shoulder while the main portion is made symmetrically concave.

Abstract: Improvements in the design of a low mass wafer holder are disclosed. The improvements include the use of peripherally located, integral lips to space a wafer or other substrate above the base plate of the wafer holder. A uniform gap is thus provided between the wafer and the base plate, such as will temper rapid heat exchanges, allow gas to flow between the wafer and wafer holder during wafer pick-up, and keep the wafer holder thermally coupled with the wafer. At the same time, thermal disturbance from lip contact with the wafer is reduced. Gas flow during pick-up can be provided through radial channels in a wafer holder upper surface, or through backside gas passages. A thicker ring is provided at the wafer holder perimeter, and is provided in some embodiments as an independent piece to accommodate stresses accompanying thermal gradients. Self-centering mechanisms are provided to keep the wafer holder centered relative to a spider which is subject to differential thermal expansion.

Abstract: An apparatus for processing a semiconductor substrate, including a process chamber having a plurality of walls and a substrate support to support the substrate within the process chamber. A radiative heat source is positioned outside the process chamber to heat the substrate through the walls when the substrate is positioned on the substrate support. In some embodiments, lenses are positioned between the heat source and the substrate to focus or diffuse radiation from the heat source and thereby selectively alter the radiation intensity incident on certain portions of the substrate. In other embodiments, diffusing surfaces are positioned between the heat source and the substrate to diffuse radiation from the heat source and thereby selectively reduce the radiation intensity incident on certain portions of the substrate.