Abstract: The disclosed embodiments provide a system that uses a DMA engine to automatically validate DMA data paths for a computing device. During operation, the system configures the DMA engine to perform a programmable DMA operation that generates a sequence of memory accesses which validate the memory subsystem and DMA paths of the computing device. For instance, the operation may include a sequence of reads and/or writes that generate sufficient data traffic to exercise the computing device's I/O controller interface and DMA data paths to memory to a specified level. The system initiates this programmable DMA operation, and then checks outputs for the operation to confirm that the operation executed successfully.

Abstract: The disclosed embodiments provide a system that uses a DMA engine to automatically validate DMA data paths for a computing device. During operation, the system configures the DMA engine to perform a programmable DMA operation that generates a sequence of memory accesses which validate the memory subsystem and DMA paths of the computing device. For instance, the operation may include a sequence of reads and/or writes that generate sufficient data traffic to exercise the computing device's I/O controller interface and DMA data paths to memory to a specified level. The system initiates this programmable DMA operation, and then checks outputs for the operation to confirm that the operation executed successfully.

Abstract: A channel time-out apparatus in a data processing system having a channel processor for controlling the allocation of a plurality of input/output channels. The channel time-out apparatus comprises a clock for generating time indications, an address generator for generating an address for each input/output channel of the plurality of input/output channels, a time-out generator for generating a time-out indicator for an input/output channel whenever that input/output channel processes an instruction, storage for storing the last time-out indicator generated by the time-out means for each input/output channel and a comparator for comparing the last time-out indicator stored in the storage for the input/output channel whose address is presently being generated by the address generator with a time indicator presently being generated by the clock for determining when a time-out event has occurred without requiring intervention by the processor.

Abstract: An apparatus and method for processing channel time-out for input/output channels in a data processing system. A counting device is provided which cycles through a count indicative, in a first part, of each of a plurality of channels in the data processing system and, in a second part, a sequence of time indications. A time indication is saved for a particular channel upon the execution of an instruction for that channel and subsequent comparisons are made of the stored time indication and the present time indication to determine if a difference in these two time indications is sufficient to constitute a time-out.