Abstract: A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.

Abstract: A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.

Abstract: A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.

Abstract: A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.

Abstract: Embodiments of the present invention are directed to computationally efficient timer-queue management. In one embodiment of the present invention, a timer queue is implemented as a circular-timer queue, containing timers, or time-associated data objects, due to expire in a relatively short period of time, and a second queue or list of timers or time-associated data objects, referred to as the “later queue,” containing timers or time-associated data objects due to expire after a period of time longer than the period of time during which the timers or timer-associated data objects on the circular-timer queue are due to expire. At generally regular intervals, as timers or time-associated data objects are removed from the circular-timer queue, timers or time-associated data objects are transferred from the later queue to the circular-timer queue.

Abstract: A media spooler system is described that provides a methodology for efficient transmission of media content from client devices, such transmission of digital images from wireless digital cameras. The media spooler or gateway addresses wireless transmission problems by acting as a protocol gateway between a thin-client device and a target host or server (supported by a server infrastructure). More particularly, the media spooler of the present invention acts as a protocol gateway between thin-client devices (e.g., “mobile visual communicator” in the form of a wireless digital camera) and server infrastructure (e.g., server-based computer systems or “Web servers” of a photographic service provider). This task entails accepting multiple, simultaneous connections from various client devices (e.g., wireless digital cameras), extracting information from those devices (e.g., digital photographs or other media content), and then uploading that information to the target server infrastructure.