Abstract: A method and apparatus is provided comprising a technology engine designed to facilitate indirect medical consultation with health care providers and create a medical record of this indirect consultation event. In one embodiment is provided a method and apparatus for capturing electronically one or more of the following: (a) patient complaints; (b) health care provider's impression/review; (c) health care provider/patient discussion of complaint symptoms following which a treatment plan is formulated regarding health care strategy; (d) any prescription issued by the health care provider; and/or (e) a set of follow-up visits by the patient.

Abstract: An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed.

Abstract: Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.

Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

Abstract: Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device. Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

Abstract: Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device. Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

Abstract: A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.

Abstract: A method and apparatus is provided comprising a technology engine designed to facilitate indirect medical consultation with health care providers and create a medical record of this indirect consultation event. In one embodiment is provided a method and apparatus for capturing electronically one or more of the following: (a) patient complaints; (b) health care provider's impression/review; (c) health care provider/patient discussion of complaint symptoms following which a treatment plan is formulated regarding health care strategy; (d) any prescription issued by the health care provider; and/or (e) a set of follow-up visits by the patient.

Abstract: A computer-based system is disclosed for pricing fixed income securities which includes a tool for selecting a portfolio of fixed income securities stored in a portfolio database, a graphical user interface for designating a pricing method for a selected fixed income security in the selected portfolio using computer readable character strings, a processor for calculating the price of the selected fixed income security based upon the designated pricing method.

Abstract: A serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Abstract: A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.

Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Abstract: An apparatus and method for pre-charging an intermediate node for high-speed wordlines for accessing memory cells in high-speed memory arrays. The apparatus pre-charges a local capacitance located between a wordline supply voltage and the wordline to a voltage level that is greater than the wordline supply voltage. Once the wordline is selected, the charge stored on the local capacitance may be quickly shared with the capacitance of the wordline. The wordline supply voltage may be applied to the local capacitance to provide small, incremental voltage to move the wordline to its final voltage thereby improving the response time of the system.

Abstract: The various embodiments of the present invention provide high precision reference devices, methods, and systems. A high precision reference device may include a plurality of reference cells to receive bias voltages and to provide a cell reference, and an averaging stage coupled to the reference cells to generate an average reference that is the average of the cell references. Other devices, methods, and systems are also claimed and described.

Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Abstract: A latch includes a switch to equalize voltages of two complementary nodes. The latch also includes at least one transistor to decouple the latch from a power supply node.

Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Abstract: A drive boost circuit provides a boosted voltage potential for driving the gate of pass device. The drive boost circuit may be one or more stages and include an inverter pair where the first inverter is powered from an operating voltage while the second inverter receives the generated boosted voltage potential that is used to drive the gate of a pass transistor.

Abstract: In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

Abstract: A computer-based system is disclosed for pricing fixed income securities which includes a tool for selecting a portfolio of fixed income securities stored in a portfolio database, a graphical user interface for designating a pricing method for a selected fixed income security in the selected portfolio using computer readable character strings, a processor for calculating the price of the selected fixed income security based upon the designated pricing method.