Abstract: Systems and methods are disclosed for a battery that includes an anode, a separator between the anode and the cathode, a cathode, and a membrane coupled to the separator having a mixed electronic conductor and ionic conductor. A method may include casting a membrane onto a surface, dispersing carbon nanotubes in acetone to form a dispersion, adding a powder and dibutyl phthalate to the dispersion to form a polymer, and mixing the polymer. Another method may include casting a sheet of a composite, removing the sheet, and rinsing the sheet. Another method may further include casting a film, evaporating to form a dry film, and casting a mixture onto the dry film to form a bilayer membrane. Another method may further include casting a cathode, casting a CNT mixture onto the cathode, evaporating the cathode, and rinsing the cathode in ether.

Abstract: Various systems and methods for capability access management are disclosed herein. In one example, a system includes a memory and a processor to send a signed custom capability description (SCCD) received from a first vendor to the memory for storage. The system may send an application received from a second vendor to the memory for storage. The system attempts to match the application to an authorization listing of the SCCD, where the application can be modified to allow access to a previously inaccessible custom capability in response to the application matching the authorization listing of the SCCD.

Abstract: Various systems and methods for capability access management are disclosed herein. In one example, a system includes a memory and a processor to send a signed custom capability description (SCCD) received from a first vendor to the memory for storage. The system may send an application received from a second vendor to the memory for storage. The system attempts to match the application to an authorization listing of the SCCD, where the application can be modified to allow access to a previously inaccessible custom capability in response to the application matching the authorization listing of the SCCD.

Abstract: A serial bus data transfer system employs an interface circuit which includes a first FIFO which receives data from a serial bus and a second FIFO which outputs data to the bus. A first processor interfaces with the FIFOs and a dual-banked shared memory comprising first and second memory banks, such that data is routed between the FIFOs and the memory banks via the first processor. A second processor interfaces with the dual-banked shared memory such that data can be bidirectionally exchanged between either memory bank and the second processor. The first memory bank can be accessed and clocked by the first processor while the second memory bank is simultaneously accessed and clocked by the second processor, and vice versa, such that data can be simultaneously transferred between the FIFOs and the second processor via the dual-banked shared memory.

Abstract: A serial bus data transfer system employs an interface circuit which includes a first FIFO which receives data from a serial bus and a second FIFO which outputs data to the bus. A first processor interfaces with the FIFOs and a dual-banked shared memory comprising first and second memory banks, such that data is routed between the FIFOs and the memory banks via the first processor. A second processor interfaces with the dual-banked shared memory such that data can be bidirectionally exchanged between either memory bank and the second processor. The first memory bank can be accessed and clocked by the first processor while the second memory bank is simultaneously accessed and clocked by the second processor, and vice versa, such that data can be simultaneously transferred between the FIFOs and the second processor via the dual-banked shared memory.