Patents by Inventor Matthew Grasse

Matthew Grasse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080300845
    Abstract: System and methods for monitoring software simulations of hardware devices optimize the monitoring of a hardware system by comparing a current software state to previously stored patterns of software states in order to disable portions of the simulation.
    Type: Application
    Filed: June 4, 2007
    Publication date: December 4, 2008
    Inventors: Mark Kostick, Dylan Dobbyn, Joshua D. Marantz, Joseph C. Tatham, JR., Jason P. Ansley, Matthew Grasse, William E. Neifert
  • Publication number: 20060085176
    Abstract: A system-level description that specifies functions performed by the components and interactions thereamong is divided into a plurality of functional blocks, each corresponding to a component. At least one of the functional blocks is selectively replaced with an optimized equivalent functional block, and the functional blocks and the at least one optimized equivalent functional block are interconnected in a manner consistent with the system-level description.
    Type: Application
    Filed: October 14, 2004
    Publication date: April 20, 2006
    Inventors: Matthew Bellantoni, William Neifert, Andrew Ladd, Matthew Grasse, Mark Kostick, Aron Atkins
  • Publication number: 20050229170
    Abstract: Integration of a system-level simulation with one or more hardware device simulations is accomplished using a mapping layer, which allows the system-level simulation to interact with the hardware device simulation at a pin level, an object level, and an abstract level. The overall simulation may operate with respect to a clock or timing device or it may operate with respect to transactions.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Inventors: Matthew Bellantoni, William Neifert, Andrew Ladd, Matthew Grasse, Mark Kostick
  • Publication number: 20050228627
    Abstract: A system-level simulation of hardware devices, each of which may have different timing requirements, utilizes one or more master objects and update objects (e.g., a clock object) in order to coordinate the device simulations. The master object may, for example, advance the update objects according to one or more criteria and then instruct an object representing a hardware device to execute.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Inventors: Matthew Bellantoni, William Neifert, Andrew Ladd, Matthew Grasse, Mark Kostick
  • Publication number: 20050228628
    Abstract: A system-level simulation of hardware devices utilizes interconnection objects to facilitate communication between a simulated device and the system, or between different simulated devices. A device may send output data to the interconnection object and/or receive input from the interconnection object. Additionally, the interconnection object may have some data-validation capability for incoming and outgoing data.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Inventors: Matthew Bellantoni, William Neifert, Andrew Ladd, Matthew Grasse, Mark Kostick