Abstract: Systems and methods for a hybrid current-mode to voltage-mode integrated circuit. An example integrated circuit embodiment configured according to this disclosure can include: a clock circuit and a logic circuit operatively synchronized with said clock circuit, where the logic circuit has a plurality of sub-circuits. The clock circuit can include a current-mode network tree and a plurality of current-mode-to-voltage-mode converters, each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being electrically connected to the current-mode network tree, and each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being associated with a respective one of the plurality of sub-circuits.

Abstract: Systems and methods for a hybrid current-mode to voltage-mode integrated circuit. An example integrated circuit embodiment configured according to this disclosure can include: a clock circuit and a logic circuit operatively synchronized with said clock circuit, where the logic circuit has a plurality of sub-circuits. The clock circuit can include a current-mode network tree and a plurality of current-mode-to-voltage-mode converters, each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being electrically connected to the current-mode network tree, and each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being associated with a respective one of the plurality of sub-circuits.

Abstract: VLSI distributed LC resonant clock networks having reduced inductor dimensions as well as simplified decoupling capacitances that are obtained by including one or more compensation capacitors. A compensation capacitor can be added in parallel with a clock capacitance and/or in parallel with a clock inductor. The presence of a compensation capacitance reduces the overhead associated with the inductor and the decoupling capacitor. The compensation capacitor (s) can be selectively switched into the network to create scalable resonant frequencies.

Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.

Abstract: A technique for implementing a clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.

Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.

Abstract: VLSI distributed LC resonant clock networks having reduced inductor dimensions as well as simplified decoupling capacitances that are obtained by including one or more compensation capacitors. A compensation capacitor can be added in parallel with a clock capacitance and/or in parallel with a clock inductor. The presence of a compensation capacitance reduces the overhead associated with the inductor and the decoupling capacitor. The compensation capacitor (s) can be selectively switched into the network to create scalable resonant frequencies.

Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.

Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.

Abstract: A technique for implementing a clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.

Abstract: A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.

Abstract: Power-efficient resonant clock meshes and multiple frequency resonant clock distribution networks.

Abstract: Methods and systems for improving the reliability of C4 solder ball contacts performed at the design stage to reduce the incidence of thermally-induced failures, including those due to electromigration and thermal cycling.

Abstract: A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.

Abstract: Methods and systems for improving the reliability of C4 solder ball contacts performed at the design stage to reduce the incidence of thermally-induced failures, including those due to electromigration and thermal cycling.

Abstract: Power-efficient resonant clock meshes and multiple frequency resonant clock distribution networks.

Abstract: A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.

Abstract: A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then sized and implemented for the VLSI clock grid. LC tanks are then placed and sized in the VLSI clock grid to implement a resonant tank clock grid and the input grid buffer is resized. A check of the resonant tank design criteria is then made. If the design criteria are met the resonant VLSI clock grid with its LC tanks is implemented. If not, another attempt at implementing a suitable LC tanks placement and sizing is made. The process iterates until a VLSI clock grid that meets the design criteria is obtained.

Abstract: Methods and systems for improving the reliability of C4 solder ball contacts performed at the design stage to reduce the incidence of thermally-induced failures, including those due to electromigration and thermal cycling.

Abstract: Methods and systems for improving the reliability of C4 solder ball contacts performed at the design stage to reduce the incidence of thermally-induced failures, including those due to electromigration and thermal cycling.