Abstract: A data security device is unitarily formed in an integrated circuit. A processor of the data security device operates in response to a clock signal provided at a clock input of the processor. Clock signal generation circuitry generates an internal clock signal. First processor-readable program code is configured to cause the processor to detect an internal, protectable, non-volatile indication of a state of the integrated circuit data security device. For example, one indication may be that non-volatile memory of the data security device has never been initialized. Another indication may be that the non-volatile memory of the data security device contains a manufacturing test pattern. Clock signal selection circuitry selectively provides a path for either the internal clock signal to be provided to the clock input of the processor or, alternatively, for an externally-provided clock signal to be provided to the clock input of the processor.

Abstract: A controller for initiating an insertion of one or more wait states on a signal bus includes registers, AND logic circuits, a counter and a OR logic circuit. One register is for connecting to a signal bus and receiving therefrom a clock signal and in response thereto receiving and latching an address strobe signal to provide a latched address strobe signal. One AND logic circuit is for receiving the latched address strobe signal, connecting to the signal bus and receiving therefrom an address write signal and a chip select signal and logically. ANDing the latched address strobe signal, the address write signal and the chip select signal to provide a first ANDed signal. Another register is for receiving a second clock signal and in response thereto receiving and latching the first ANDed signal to provide a first latched ANDed signal. Another AND logic circuit is for receiving and logically ANDing the first latched ANDed signal and a decoded address signal to provide a second ANDed signal.

Abstract: According to the present invention, the solution includes the hardware hash algorithm block to automatically generate data to hash from its initialization values and to run unassisted instead of needing a continuous supply of additional input data. This approach according to the present invention solves the above shortcomings of related solutions by eliminating the need to continuously feed input data to be hashed to obtain a high fault coverage. This reduces the sizes of the firmware and test vectors necessary to test the hardware. Also, since the hardware autonomously generates new data to hash, other hardware modules can be tested in parallel. This reduces the overall test time and cost. To remove the requirement of inputting multiple fixed length sub-blocks, additional sub-blocks are created from the initial sub-block using a hardware expansion function, and the hardware continues to run unattended for some predetermined number of sub-blocks.

Abstract: An iterative logic circuit for iteratively performing a logic function includes a two-input logic gate and a D-type flip-flop. The flip-flop receives and time-delays the output signal from the logic gate to provide a feedback signal as one of the input signals to the logic gate. By sequentially processing the feedback signal together with a serial input data signal, the logic gate iteratively performs an associative logic function (e.g. EXCLUSIVE-OR) upon the serial input data signal, thereby performing a parallel logic function by executing a serial logic operation.

Abstract: A method of securely testing a cryptographic device need not be carried out in a secure testing facility by cleared personnel. First, a test cycle total count number is provided. Then, for each of a plurality of test cycles, the number being determined from the test cycle total count number, an input data signal is provided to the cryptographic device. The input data signal is encrypted to determine an encrypted signal, and the encrypted signal is then decrypted to determine a decrypted signal. Finally, the input data signal is compared to the decrypted signal. A cryptographic device includes receiving circuitry for receiving the input data signal and encryption circuitry that encrypts the input data signal to determine the encrypted signal. Decryption circuitry decrypts the encrypted signal to determine a decrypted signal, and comparing circuitry compares the input data signal to the decrypted signal.

Abstract: A data security device is unitarily formed in an integrated circuit. A processor of the data security device operates in response to a clock signal provided at a clock input of the processor. Clock signal generation circuitry generates an internal clock signal. First processor-readable program code is configured to cause the processor to detect an internal, protectable, non-volatile indication of a state of the integrated circuit data security device. For example, one indication may be that non-volatile memory of the data security device has never been initialized. Another indication may be that the non-volatile memory of the data security device contains a manufacturing test pattern. Clock signal selection circuitry selectively provides a path for either the internal clock signal to be provided to the clock input of the processor or, alternatively, for an externally-provided clock signal to be provided to the clock input of the processor.

Abstract: A reset and clock circuit for providing a valid power-up reset signal prior to distribution of a clock signal includes power sensing circuitry, a clock generator and a reset generator. The power sensing circuitry monitors the power supply voltage and generates a power-up signal which is asserted when it has risen above a predetermined value. The power sensing circuitry also receives a clock signal and, in accordance with the power-up and clock signals, provides a number of power status signals. One of the power status signals is asserted in response to assertion of the power-up signal, while another is asserted in response to reception of a group of clock signal pulses. The clock generator, in response to assertion of the first power status signal, provides the clock signal. The reset generator, in accordance with the power status signals and clock signal, provides a number of reset signals each one of which is initially asserted prior to the providing of the clock signal by the clock signal generator.