Abstract: Disclosed are compounds having structural formulas (I)-(XI), and related pharmaceutical compositions. Also disclosed are methods of selecting and treating human subjects suffering from a kidney disease, using the compounds of formulas (I)-(XI), and methods of determining the efficacy of TRPC5 inhibitor therapies using the same.

Abstract: Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.

Abstract: Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.

Abstract: Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.

Abstract: Computer system and method using a Kautz-like digraph to interconnect computer nodes and having control back channel between nodes. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn?1; The data interconnections from a node x to a node y in the topology satisfy the relationship y=(?x*k?j) mod O, where 1?j?k; and each x,y pair includes a unidirectional control link from node y to node x to convey flow control and error information from a receiving node y to a transmitting node x.

Abstract: Computer systems and methods using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn?1. The interconnections from a node x to a node y in the topology satisfy the relationship y=(?x*k?j) mod O, where 1?j?k, and the computing nodes are arranged onto a plurality of modules. Each module has an equal plurality of computing nodes on it. A majority of the inter-node connections are contained on the plurality of modules and a minority of the inter-node connections are inter-module connections. Inter-module connections are routed among modules in parallel on an inter-module connection plane.

Abstract: Computer systems and methods using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn?1. The interconnections from a node x to a node y in the topology satisfy the relationship y=(?x*k?j) mod O, where 1?j?k, and the computing nodes are arranged onto a plurality of modules. Each module has an equal plurality of computing nodes on it. A majority of the inter-node connections are contained on the plurality of modules and a minority of the inter-node connections are inter-module connections. Inter-module connections are routed among modules in parallel on an inter-module connection plane.

Abstract: Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.

Abstract: Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.

Abstract: Large scale computing systems with multi-lane mesochronous data transfers among computer nodes. A large scale computing system includes a large plurality of computing nodes interconnected in a predefined topology. Each computing node is controlled by a corresponding clock signal, and the each clock signal has a mesochronous relationship to the clock signals on the other computing nodes. Each connection between nodes is a multi-lane connection, and each lane carries a serial stream of data that is mesochronously related to the other lanes. Each data lane is characterized relative to the other data lanes between the first and second node to determine relative delay in transmission between the first and second nodes. The transmission delays are equalized so that each data lane provides data for processing in the second clock domain in substantial synchronism with the other lanes.

Abstract: The invention relates to a systems and methods for remote direct memory access to processor caches for remote direct memory access (RDMA) reads and writes. One aspect of the invention is a computer node within a multi-node computer system having a plurality of interconnected processing nodes. The computer node has least one processor associated with at least one processor cache for holding cache entries for the at least one processor. A cache interface for the remote DMA engine on the node includes logic to consult the processor cache control structure, to determine whether the processor cache has a cache entry associated with a physical address of a DMA transfer, and if so, reading from that cache entry or writing to that cache entry to service the DMA transfer.

Abstract: Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.

Abstract: Computer system and method using a Kautz-like digraph to interconnect computer nodes and having control back channel between nodes. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)kn?1; The data interconnections from a node x to a node y in the topology satisfy the relationship y=(?x*k?j) mod O, where 1?j?k; and each x,y pair includes a unidirectional control link from node y to node x to convey flow control and error information from a receiving node y to a transmitting node x.

Abstract: A large-scale multiprocessor system with a link-level interconnect that provides in-order packet delivery. The method comprises transmitting, over a link in the defined interconnection topology, a sequence of packets in a defined order from a first node to a second node. The second node is an intermediate node in a route between the first and third node. At the first node, the transmitted packets are stored in a buffer. In response to an error in reception, the first node retrieves packets from the buffer and re-transmits them to the second node, beginning with the packet subsequent to the last packet in the sequence correctly received by the second node and continuing through the remainder of the sequence of packets.

Abstract: An exception handler for a processor is split into two functional units to permit exceptions to be classified into two categories. The first category of exceptions includes performance critical excepted instructions, while the second category includes non-performance critical excepted instructions. The performance critical exceptions are routed to a speculative exception handler, which resolves the exceptions speculatively, even though the excepted instruction may lie in a speculative path of the program flow. The non-performance critical exceptions are routed to a non-speculative exception handler that only resolves exceptions when the excepted instruction is certain to execute in an actual path of the program flow.

Abstract: Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.

Abstract: Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.

Abstract: Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.

Abstract: An exception handler for a processor is split into two functional units to permit exceptions to be classified into two categories. The first category of exceptions includes performance critical excepted instructions, while the second category includes non-performance critical excepted instructions. The performance critical exceptions are routed to a speculative exception handler, which resolves the exceptions speculatively, even though the excepted instruction may lie in a speculative path of the program flow. The non-performance critical exceptions are routed to a non-speculative exception handler that only resolves exceptions when the excepted instruction is certain to execute in an actual path of the program flow.

Abstract: Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.