Patents by Inventor Matthew Hansen Childs

Matthew Hansen Childs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Meeting setup/hold times for a repetitive signal relative to a clock
    Patent number: 10775833
    Abstract: Clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock with active and inactive clock edges within a clock period, and signal capture circuitry to capture repetitive signal transitions at an active clock edge, based on pre-defined setup and hold times which determine a setup/hold window. Clock phase adjustment circuitry is configured to adjust clock phase so that the repetitive signal transitions occur within a signal capture window between setup/hold windows. Clock phase adjustment can be based on: aligning the clock inactive edges to the repetitive signal transitions; and/or averaging successive phase comparisons of the clock and the repetitive signal transitions; and/or selectively performing an initial polarity inversion to generate a polarity inverted clock, and then adjusting clock phase of the polarity inverted clock. An example implementation is JESD204B (subclass1) to adjust DEVCLK phase relative to a SYSREF timing reference control signal.
    Type: Grant
    Filed: March 4, 2018
    Date of Patent: September 15, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Paul Joseph Kramer, Matthew Hansen Childs, Robert Callaghan Taft
  • MEETING SETUP/HOLD TIMES FOR A REPETITIVE SIGNAL RELATIVE TO A CLOCK
    Publication number: 20180253122
    Abstract: Clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock with active and inactive clock edges within a clock period, and signal capture circuitry to capture repetitive signal transitions at an active clock edge, based on pre-defined setup and hold times which determine a setup/hold window. Clock phase adjustment circuitry is configured to adjust clock phase so that the repetitive signal transitions occur within a signal capture window between setup/hold windows. Clock phase adjustment can be based on: aligning the clock inactive edges to the repetitive signal transitions; and/or averaging successive phase comparisons of the clock and the repetitive signal transitions; and/or selectively performing an initial polarity inversion to generate a polarity inverted clock, and then adjusting clock phase of the polarity inverted clock. An example implementation is JESD204B (subclass1) to adjust DEVCLK phase relative to a SYSREF timing reference control signal.
    Type: Application
    Filed: March 4, 2018
    Publication date: September 6, 2018
    Inventors: Paul Joseph Kramer, Matthew Hansen Childs, Robert Callaghan Taft