Patents by Inventor Matthew Heath

Matthew Heath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260006037
    Abstract: A method for discontinuing interaction processing using an enumeration detection system may include receiving data associated with a plurality of interaction instances. The plurality of interaction instances may be associated with an entity. The method may further include extracting one or more interaction features from the data. The method may further include providing the one or more interaction features to a determinative machine-learning model. The determinative machine-learning model may be trained to identify enumeration patterns and output an enumeration score based on the identified enumeration patterns. The method may further include determining that the enumeration score exceeds a predetermined threshold. The method may further include discontinuing interaction processing for the entity based on the enumeration score exceeding the predetermined threshold.
    Type: Application
    Filed: June 26, 2024
    Publication date: January 1, 2026
    Inventors: Matthew HEATH, Robert BERGELT
  • Patent number: 7917823
    Abstract: A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: David Dehnert, Matthew Heath
  • Publication number: 20100169728
    Abstract: A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventors: David Dehnert, Matthew Heath