Abstract: A connector shell includes a frame, a dividing wall and a plurality of connector inserts. The frame surrounds a periphery of the shell. The dividing wall is homogeneously formed with the frame and separates a plurality of recesses. The connector inserts are homogeneously formed with the frame and the dividing wall. The inserts are disposed with one or more of the recesses. Each insert includes a body and a plurality of cavities. Each body is configured to hold a plurality of contacts that protrude from each of a mating and a loading side. The contacts are configured to be mounted to a circuit board in a location proximate to the loading side and to mate with a plurality of other electrical connectors in a location proximate to the mating side.

Abstract: Techniques for performing physical verification processes for stacked integrated circuit devices. An interface between a first two-dimensional integrated circuit device and a second two-dimensional integrated circuit device is identified. The design data for the identified layers in the first and second two-dimensional integrated circuit devices are then combined and physically verified as a single set of interface design data. The design data for the first two-dimensional integrated circuit device and the second two-dimensional integrated circuit device are then separately physically verified. Once the interface design data, the first two-dimensional integrated circuit device design data and the second two-dimensional integrated circuit device design data have been physically verified, the verified design can be recombined to form verified design data corresponding to a stacked integrated circuit device.

Abstract: Techniques for assisting a designer in correcting discrepancies identified in layout design data. A user interface may be provided listing identified shorts and relevant information related to those shorts. Still further, the user interface may allow a designer to selectively choose a subset of the identified shorts, and to designate or otherwise provide correction data for use to correct the shorts before performing a short isolation process on the selected shorts. Alternately or additionally a user interface may provide a designer with graphical images showing the correction that should be made by a designer to address an identified discrepancy in layout design data.

Abstract: A connector shell includes a frame, a dividing wall and a plurality of connector inserts. The frame surrounds a periphery of the shell. The dividing wall is homogeneously formed with the frame and separates a plurality of recesses. The connector inserts are homogeneously formed with the frame and the dividing wall. The inserts are disposed with one or more of the recesses. Each insert includes a body and a plurality of cavities. Each body is configured to hold a plurality of contacts that protrude from each of a mating and a loading side. The contacts are configured to be mounted to a circuit board in a location proximate to the loading side and to mate with a plurality of other electrical connectors in a location proximate to the mating side.

Abstract: Printed circuit board, ASIC, transistor group, or other circuit timing can be analyzed by symbolically modeling the circuit, simulating the behavior of the circuit, analyzing the behavior to catch timing violations. Routing constraints for critical traces can be made by using the analysis results as the input to a trace circuit router. Further timing verification of the printed circuit board, ASIC, transistor group, or other circuit layout may be accomplished by analyzing and modeling the interconnect delays of the traces, simulating the symbolic circuit model with the interconnect delay model, and analyzing the behavior of the circuit for timing violations.

Abstract: Printed circuit board, ASIC, transistor group, or other circuit timing can be analyzed by symbolically modeling the circuit, simulating the behavior of the circuit, analyzing the behavior to catch timing violations. Routing constraints for critical traces can be made by using the analysis results as the input to a trace circuit router. Further timing verification of the printed circuit board, ASIC, transistor group, or other circuit layout may be accomplished by analyzing and modeling the interconnect delays of the traces, simulating the symbolic circuit model with the interconnect delay model, and analyzing the behavior of the circuit for timing violations.

Abstract: Methods and apparatus for matching database entries in an electronic design automation environment is disclosed. The disclosed technology may be applied, for instance, to import data (e.g., attributes or rules) from an EDA design database to an altered version of the EDA design database or to import data from a master database to an EDA design database. In one aspect, a match made between a first database entry and a second database entry is verified by comparing the second database entry to multiple entries of the first database, thereby helping to ensure that the first database entry is the best match for the second database entry. The matching may be performed using a similarity-based matching method. In another aspect, multiple criteria are used to determine whether a match exists between database entries and whether certain data should be imported between the databases.

Abstract: A fixture for releasable retaining at least one lenticular article in a fixed orientation while the article(s) is/are being subjected to one or more applications of a thin film coating process comprises a perforated metallic sheet having at least one aperture therein adapted to receive the article(s). The thickness of the metal fixture bears a ratio to the size of the articles being retained that is within a particular range. A method for applying thin film optical coatings to lenticular articles utilizing such a fixture is also disclosed.

Abstract: A fixture for releasably retaining at least one lenticular article in a fixed orientation while the article(s) is/are being subjected to one or more applications of a thin film coating process comprises a perforated metallic sheet having at least one aperture therein adapted to receive the article(s). The thickness of the metal fixture bears a ratio to the size of the articles being retained that is within a particular range. A method for applying thin film optical coatings to lenticular articles utilizing such a fixture is also disclosed.