Patents by Inventor Matthew J. Adiletta

Matthew J. Adiletta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12219706
    Abstract: Examples described herein relate to an apparatus that includes a flexible conductor covered in an insulative material and at least one conductor region in contact with the flexible conductor. In some examples, melting of the at least one conductor region is to cause a conductive coupling of the flexible conductor with a second conductor and wherein the flexible conductor is adapted to conductively couple a first circuit board oriented orthogonal to a second circuit board. In some examples, the at least one conductor region comprises at least one solder ball of a grid array. In some examples, the at least one conductor region is re-solderable.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: February 4, 2025
    Assignee: Intel Corporation
    Inventors: Jonathan W. Thibado, Aaron Gorius, Michael T. Crocker, Matthew J. Adiletta, John C. Gulick, Emery E. Frey
  • Patent number: 12111775
    Abstract: Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: October 8, 2024
    Assignee: Intel Corporation
    Inventors: Duane E. Galbi, Matthew J. Adiletta, Hugh Wilkinson, Patrick Connor
  • Patent number: 12099408
    Abstract: An apparatus is described. The apparatus includes a memory controller having logic circuitry to write a unit of write data into a plurality of memory chips according to a striping pattern that includes multiple protected sub words, each protected sub word including a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: September 24, 2024
    Assignee: Intel Corporation
    Inventors: Duane E. Galbi, Matthew J. Adiletta
  • Patent number: 12082370
    Abstract: Examples described herein relate to a system. The system can include a container that contains fluid to provide two phase immersion liquid cooling (2PILC) for a system within the container. The container can enclose a first circuit board with a first side of the first circuit board is conductively coupled to at least one device. The container can enclose a motherboard conductively coupled to a second side of the first circuit board with a first side of the motherboard is conductively coupled to the second side of the first circuit board. The motherboard can include at least four edges. Connectors can conductively connect the motherboard with a second circuit board. The second circuit board can include at least four edges and an edge of the motherboard is oriented approximately 90 degrees to an edge of the second circuit board. At least one device can include one or more of: a processor, memory device, accelerator device, or network interface.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Aaron Gorius, Michael T. Crocker, Jonathan W. Thibado, Matthew J. Adiletta, John C. Gulick, Emery E. Frey
  • Publication number: 20240214279
    Abstract: Examples described herein relate to determining whether to process or not process data based on a reliability metric. For example, based on receiving a response to a request to a first microservice, with the reliability metric, from one or more servers, a decision can be made of whether to process, by a second microservice, a result associated with the response based on the reliability metric. In some examples, the reliability metric comprises an indicator of memory health and computational accuracy.
    Type: Application
    Filed: February 5, 2024
    Publication date: June 27, 2024
    Inventors: Matthew J. ADILETTA, Zane BALL, Susanne M. BALLE, Patrick CONNOR
  • Publication number: 20230305720
    Abstract: Examples described herein relate to a memory controller, when connected to at least one memory device in a multi-tiered memory system comprising a near memory and far memory, is to allocate a region of the near memory to a requester based on receipt of a request. In some examples, the memory controller includes circuitry to transmit at least one memory read command and address information to the multi-tiered memory system to read data from the multi-tiered memory system and circuitry to transmit at least one memory write command and address information to the multi-tiered memory system to write data to the multi-tiered memory system, wherein the near memory comprises at least one memory connected to the memory controller via a memory interface and the far memory comprises at least one memory connected to the memory controller via a network.
    Type: Application
    Filed: December 19, 2022
    Publication date: September 28, 2023
    Inventors: Slawomir PUTYRSKI, Matthew J. ADILETTA
  • Publication number: 20230215493
    Abstract: Methods and apparatus for Cross DRAM DIMM sub-channel pairing. Memory channels on a memory controller or System on a Chip (SoC) are segmented into two subchannels, each including Command and Address (C/A) signals, DQ (data) lines. Under different solutions the two subchannels may share a command-bus clock or use separate command-bus clocks. Some approaches use subchannels from different memory channels to provide the C/A and DQ lines for two subchannels to a given DIMM. One solution implements an additional command-bus clock on the DIMM connector repurposing existing MCR pins to provide command-bus clock signals to a Registered Clock Driver (RCD) to allow the subchannels to be fully independent. Another solution is the pair every other DRAM controller to the same command-bus clock. Other solutions employ Skip-1, Skip-2, and Skip-3 configurations under which the clocks for the DDR-IO circuitry are not logically co-located with the subchannel IO circuitry.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: Duane E. GALBI, Matthew J. ADILETTA, Mohammad M. RASHID, Todd HINCK, Vijaya K. BODDU
  • Publication number: 20230100935
    Abstract: Examples described herein relate to circuitry to perform load balancing; at least one memory; and at least one processor. In some examples, at least one processor is to execute instructions stored in the at least one memory that cause the at least one processor to: execute a communication proxy that is to allocate packet data to the circuitry to perform load balancing to allocate workloads among cores and allocate received and transmitted remote procedure calls to at least one queue in circuitry to queue one or more packets.
    Type: Application
    Filed: December 5, 2022
    Publication date: March 30, 2023
    Inventors: Kelley MULLICK, Mrittika GANGULI, Brian P. JOHNSON, Matthew J. ADILETTA
  • Patent number: 11349734
    Abstract: Examples may include racks for a data center and sleds for the racks, the sleds arranged to house physical resources for the data center. The sleds and racks can be arranged to be autonomously manipulated, such as, by a robot. The sleds and racks can include features to facilitate automated installation, removal, maintenance, and manipulation by a robot.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Michael T. Crocker
  • Publication number: 20220107741
    Abstract: Racks and rack pods to support a plurality of sleds are disclosed herein. Switches for use in the rack pods are also disclosed herein. A rack comprises a plurality of sleds and a plurality of electromagnetic waveguides. The plurality of sleds are vertically spaced from one another. The plurality of electromagnetic waveguides communicate data signals between the plurality of sleds.
    Type: Application
    Filed: December 13, 2021
    Publication date: April 7, 2022
    Inventors: Matthew J. ADILETTA, Myles WILDE, Aaron GORIUS, Michael T. CROCKER, Paul H. DORMITZER, Mark A. SCHMISSEUR
  • Patent number: 11237840
    Abstract: All in one mobile computing devices and methods performed by the devices. The all in one mobile computing device includes a processor, memory, and software instructions configured to be executed on the processor to enable the mobile computing device to perform various operations. The all in one device may include various wired and wireless interfaces that enable it to communicate with a wide-range of devices, including smartphones, tablets, laptops, personal computers, smart TVs, and others. The all in one device is capable of being remotely accessed when linked in communication with a second device, and is enabled to aggregate data from various user devices and cloud-based services to create unified data resources. Data that is accessed by the device may be synched with a cloud-based storage service to enable a user to access data from across a range of devices via the all in one device.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Myles Wilde, Michael F. Fallon, Amit Kumar, Chengda Yang, Aaron Gorius, William R. Wheeler
  • Patent number: 11233712
    Abstract: Technologies for connecting data cables in a data center are disclosed. In the illustrative embodiment, racks of the data center are grouped into different zones based on the distance from the racks in a given zone to a network switch. All of the racks in a given zone are connected to the network switch using data cables of the same length. In some embodiments, certain physical resources such as storage may be placed in racks that are in zones closer to the network switch and therefore use shorter data cables with lower latency. An orchestrator server may, in some embodiments, schedule workloads or create virtual servers based on the different zones and corresponding latency of different physical resources.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Michael T. Crocker
  • Publication number: 20210400813
    Abstract: Examples described herein relate to an apparatus that includes a flexible conductor covered in an insulative material and at least one conductor region in contact with the flexible conductor. In some examples, melting of the at least one conductor region is to cause a conductive coupling of the flexible conductor with a second conductor and wherein the flexible conductor is adapted to conductively couple a first circuit board oriented orthogonal to a second circuit board. In some examples, the at least one conductor region comprises at least one solder ball of a grid array. In some examples, the at least one conductor region is re-solderable.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 23, 2021
    Inventors: Jonathan W. THIBADO, Aaron GORIUS, Michael T. CROCKER, Matthew J. ADILETTA, John C. GULICK, Emery E. FREY
  • Patent number: 11200104
    Abstract: Racks and rack pods to support a plurality of sleds are disclosed herein. Switches for use in the rack pods are also disclosed herein. A rack comprises a plurality of sleds and a plurality of electromagnetic waveguides. The plurality of sleds are vertically spaced from one another. The plurality of electromagnetic waveguides communicate data signals between the plurality of sleds.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Myles Wilde, Aaron Gorius, Michael T. Crocker, Paul H. Dormitzer, Mark A. Schmisseur
  • Publication number: 20210385971
    Abstract: Examples described herein relate to a system. The system can include a container that contains fluid to provide two phase immersion liquid cooling (2PILC) for a system within the container. The container can enclose a first circuit board with a first side of the first circuit board is conductively coupled to at least one device. The container can enclose a motherboard conductively coupled to a second side of the first circuit board with a first side of the motherboard is conductively coupled to the second side of the first circuit board. The motherboard can include at least four edges. Connectors can conductively connect the motherboard with a second circuit board. The second circuit board can include at least four edges and an edge of the motherboard is oriented approximately 90 degrees to an edge of the second circuit board. At least one device can include one or more of: a processor, memory device, accelerator device, or network interface.
    Type: Application
    Filed: June 2, 2021
    Publication date: December 9, 2021
    Inventors: Aaron GORIUS, Michael T. CROCKER, Jonathan W. THIBADO, Matthew J. ADILETTA, John C. GULICK, Emery E. FREY
  • Patent number: 11108574
    Abstract: Technologies for switch link and ply management for variable oversubscription ratios include powering up and down links of one or more network plys according to bandwidth demand, desired oversubscription ratio and/or other parameters. Telemetry data representing one or more network traffic metrics of one or more switch plies is monitored to determine respective power states of the plurality of links associated with the one or more switch plies as a function of a desired oversubscription ratio calculated based on the telemetry data. The respective power state of the plurality of links is set accordingly.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Mrittika Ganguli, Joe Carvalho, Gary Muntz, Matthew J. Adiletta
  • Patent number: 11071039
    Abstract: Examples may include a management authority for a software-define network (SDN) receiving telemetric data from wireless devices coupled together in a mesh network having one or more ad hoc connections between the wireless devices. The management authority may then generate a routing table based on the received telemetric data and provide a routing table for use by the wireless devices to route data within the mesh network or route data to a network coupled to the mesh network.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 20, 2021
    Assignee: INTEL CORPORATION
    Inventors: Michael F. Fallon, Matthew J. Adiletta
  • Publication number: 20210209035
    Abstract: Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub.
    Type: Application
    Filed: March 25, 2021
    Publication date: July 8, 2021
    Inventors: Duane E. GALBI, Matthew J. ADILETTA, Hugh WILKINSON, Patrick CONNOR
  • Publication number: 20210200667
    Abstract: Examples described herein relate to memory thin provisioning in a memory pool of one or more dual in-line memory modules or memory devices. At any instance, any central processing unit (CPU) can request and receive a full virtual allocation of memory in an amount that exceeds the physical memory attached to the CPU (near memory). A remote pool of additional memory can be dynamically utilized to fill the gap between allocated memory and near memory. This remote pool is shared between multiple CPUs, with dynamic assignment and address re-mapping provided for the remote pool. To improve performance, the near memory can be operated as a cache of the pool memory. Inclusive or exclusive content storage configurations can be applied. An inclusive cache configuration can include an entry in a near memory cache also being stored in a memory pool whereas an exclusive cache configuration can provide an entry in either a near memory cache or in a memory pool but not both.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Inventors: Debra BERNSTEIN, Hugh WILKINSON, Douglas CARRIGAN, Bassam N. COURY, Matthew J. ADILETTA, Durgesh SRIVASTAVA, Lidia WARNES, William WHEELER, Michael F. FALLON
  • Publication number: 20210191811
    Abstract: An apparatus is described. The apparatus includes a memory controller having logic circuitry to write a unit of write data into a plurality of memory chips according to a striping pattern that includes multiple protected sub words, each protected sub word including a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 24, 2021
    Inventors: Duane E. GALBI, Matthew J. ADILETTA