Patents by Inventor Matthew J. Byom
Matthew J. Byom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160092110Abstract: Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up.Type: ApplicationFiled: December 8, 2015Publication date: March 31, 2016Inventors: Vadim Khmelnitsky, Daniel J. Post, Nir Jacob Wakrat, Matthew J. Byom, Kenneth L. Herman, Alexander C. Sanks
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Patent number: 9235502Abstract: Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up.Type: GrantFiled: September 16, 2011Date of Patent: January 12, 2016Assignee: APPLE INC.Inventors: Vadim Khmelnitsky, Daniel J. Post, Nir Jacob Wakrat, Matthew J. Byom, Kenneth Herman, Alexander Sanks
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Patent number: 9208116Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.Type: GrantFiled: January 12, 2015Date of Patent: December 8, 2015Assignee: Apple Inc.Inventors: Joseph Sokol, Jr., Manoj Radhakrishnan, Matthew J. Byom, Robert Hoopes, Christopher Sarcone
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Publication number: 20150347327Abstract: In one embodiment, input-output (I/O) scheduling system detects and resolves priority inversions by expediting previously dispatched requests to an I/O subsystem. In response to detecting the priority inversion, the system can transmit a command to expedite completion of the blocking I/O request. The pending request can be located within the I/O subsystem and expedited to reduce the pendency period of the request.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: Apple Inc.Inventors: Russell A. BLAINE, Kushal DALMIA, Joseph SOKOL, JR., Andrew W. VOGAN, Matthew J. BYOM
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Patent number: 9146821Abstract: Systems and methods are disclosed for monitoring the time it takes to perform a write operation, and based on the time it takes, a determination is made whether to retire a block that is a recipient of the write operation. The time duration of the write operation for a page or a combination of pages may indicate whether any block or blocks containing the page or combination of pages is experiencing a physical failure. That is, if the time duration of the write operation for a particular page exceeds time threshold, this may indicate that this page requires a larger number of program cycles than other pages. The longer programming cycle can be an indication of cell leakage or a failing block.Type: GrantFiled: May 1, 2014Date of Patent: September 29, 2015Assignee: APPLE INC.Inventors: Matthew J. Byom, Nir J. Wakrat
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Patent number: 9069660Abstract: Systems and methods for writing to high-capacity memory are disclosed. In high-capacity memory systems in which the capacity of the characteristic portion of the memory (e.g., a page of NAND flash memory) exceeds the capacity of a buffer used to write to the memory, underutilization issues are prevalent. Data organized in the buffer can be combined with additional data to improve utilization of the characteristic portion. According to various embodiments, the additional data can include duplicate copies of the data, whitened data, or any other suitable type of data.Type: GrantFiled: March 15, 2013Date of Patent: June 30, 2015Assignee: APPLE INC.Inventors: Nir Jacob Wakrat, Matthew J. Byom
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Patent number: 9063732Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.Type: GrantFiled: November 11, 2013Date of Patent: June 23, 2015Assignee: APPLE INC.Inventors: Matthew J. Byom, Vadim Khmelnitsky, Hugo B. Fiennes, Arjun Kapoor
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Publication number: 20150127863Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.Type: ApplicationFiled: January 12, 2015Publication date: May 7, 2015Inventors: Joseph Sokol, JR., Manoj Radhakrishnan, Matthew J. Byom, Robert Hoopes, Christopher Sarcone
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Patent number: 8959263Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.Type: GrantFiled: January 8, 2013Date of Patent: February 17, 2015Assignee: Apple Inc.Inventors: Joseph Sokol, Jr., Manoj Radhakrishnan, Matthew J. Byom, Robert Hoopes, Christopher Sarcone
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Patent number: 8949512Abstract: Systems and methods are disclosed for trim token journaling. A device can monitor the order in which trim commands and write commands are applied to an indirection system stored in a volatile memory of the device. In some embodiments, the device can directly write to a page of an NVM with a trim token that indicates that a LBA range stored in the page has been trimmed. In other embodiments, a device can add pending trim commands to a trim buffer stored in the volatile memory. Then, when the trim buffer reaches a pre-determined threshold or a particular trigger is detected, trim tokens associated with all of the trim commands stored in the trim buffer can be written to the NVM. Using these approaches, the same sequence of events that was applied to the indirection system during run-time can be applied during device boot-up.Type: GrantFiled: February 17, 2012Date of Patent: February 3, 2015Assignee: Apple Inc.Inventors: Andrew W. Vogan, Matthew J. Byom, Daniel J. Post
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Patent number: 8918655Abstract: Systems, apparatuses, and methods are provided for whitening and managing data for storage in non-volatile memories, such as Flash memory. In some embodiments, an electronic device such as media player is provided, which may include a system-on-a-chip (SoC) and a non-volatile memory. The SoC may include SoC control circuitry and a memory interface that acts as an interface between the SoC control circuitry and the non-volatile memory. The SoC can also include an encryption module, such as a block cipher based on the Advanced Encryption Standard (AES). The memory interface can direct the encryption module to whiten all types of data prior to storage in the non-volatile memory, including sensitive data, non-sensitive data, and memory management data. This can, for example, prevent or reduce program-disturb problems or other read/write/erase reliability issues.Type: GrantFiled: November 18, 2013Date of Patent: December 23, 2014Assignee: Apple Inc.Inventors: Kenneth L. Herman, Matthew J. Byom, Michael J. Smith, Tahoma M. Toelkes
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Publication number: 20140344609Abstract: Systems and methods are disclosed for dynamically allocating power for a system having non-volatile memory. A power budgeting manager of a system can determine if the total amount of power available for the system is below a pre-determined power level (e.g., a low power state). While the system is operating in the low power state, the power budgeting manager can dynamically allocate power among various components of the system (e.g., a processor and non-volatile memory).Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Nir J. Wakrat, Kenneth L. Herman, Matthew J. Byom
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Patent number: 8886963Abstract: Systems and methods are disclosed for secure relocation of encrypted files for a system having non-volatile memory (“NVM”). A system can include an encryption module that is configured to use a temporary encryption seed (e.g., a randomly generated key and a corresponding initialization vector) to decrypt and encrypt data files in an NVM. These data files may have originally been encrypted with different encryption seeds. Using such an approach, data files can be securely relocated even if the system does not have access to the original encryption seeds. In addition, the temporary encryption seed allows the system to bypass a default key scheme.Type: GrantFiled: September 15, 2011Date of Patent: November 11, 2014Assignee: Apple Inc.Inventors: Conrad Sauerwald, Daniel J. Post, Eric Brandon Tamura, Matthew J. Byom, Puja Dilip Gupta
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Publication number: 20140281136Abstract: Systems and methods for writing to high-capacity memory are disclosed. In high-capacity memory systems in which the capacity of the characteristic portion of the memory (e.g., a page of NAND flash memory) exceeds the capacity of a buffer used to write to the memory, underutilization issues are prevalent. Data organized in the buffer can be combined with additional data to improve utilization of the characteristic portion. According to various embodiments, the additional data can include duplicate copies of the data, whitened data, or any other suitable type of data.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: APPLE INC.Inventors: Nir Jacob Wakrat, Matthew J. Byom
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Publication number: 20140281588Abstract: Systems and methods are disclosed for generating efficient reads for a system having non-volatile memory (“NVM”). A read command can be separated by a host processor of the system into two phases: a) transmitting a command to a storage processor of the system, where the command is associated with one or more logical addresses, and b) generating data transfer information. The host processor can generate the data transfer information while the storage processor is processing the command from the host processor. Once the data transfer information has been generated and data has been read from the NVM, the data can be transferred.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: Apple Inc.Inventors: Andrew W. Vogan, Matthew J. Byom, Alexander C. Sanks, Daniel J. Post, Hari Hara Kumar Maharaj, Nir Jacob Wakrat, Kenneth L. Herman
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Publication number: 20140245084Abstract: Systems and methods are disclosed for monitoring the time it takes to perform a write operation, and based on the time it takes, a determination is made whether to retire a block that is a recipient of the write operation. The time duration of the write operation for a page or a combination of pages may indicate whether any block or blocks containing the page or combination of pages is experiencing a physical failure. That is, if the time duration of the write operation for a particular page exceeds time threshold, this may indicate that this page requires a larger number of program cycles than other pages. The longer programming cycle can be an indication of cell leakage or a failing block.Type: ApplicationFiled: May 1, 2014Publication date: August 28, 2014Applicant: Apple Inc.Inventors: Matthew J. Byom, Nir J. Wakrat
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Publication number: 20140192599Abstract: Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to run a test of the memory locations in the test region. The results of the test may be stored in the general purpose region. At the completion of the test, the test results may be provided from the general purpose region and displayed to a user. The virtual partitions may be removed prior to shipping the electronic device for distribution.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: Apple Inc.Inventors: Matthew J. Byom, Nir J. Wakrat, Kenneth L. Herman
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Publication number: 20140195699Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.Type: ApplicationFiled: January 8, 2013Publication date: July 10, 2014Applicant: Apple Inc.Inventors: Joseph Sokol, JR., Manoj Radhakrishnan, Matthew J. Byom, Robert Hoopes, Christopher Sarcone
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Patent number: 8737148Abstract: Systems and methods are provided for selectively retiring blocks based on refresh events of those blocks. In addition to refresh events, other criteria may be applied in making a decision whether to retire a block. By applying the criteria, the system is able to selectively retire blocks that may otherwise continue to be refreshed.Type: GrantFiled: March 15, 2013Date of Patent: May 27, 2014Assignee: Apple Inc.Inventors: Matthew J. Byom, Daniel J. Post, Vadim Khmelnitsky
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Patent number: 8732392Abstract: Systems and methods are provided for storing data in a portion of a non-volatile memory (“NVM”) such that the status of the NVM portion can be determined with high probability on a subsequent read. An NVM interface, which may receive write commands to store user data in the NVM, can store a fixed predetermined sequence (“FPS”) with the user data. The FPS may ensure that a successful read operation on a NVM portion is not misinterpreted as a failed read operation or as an erased NVM portion. For example, if the NVM returns an all-zero vector when a read request fails, the FPS can include at least one “1” or one “0”, as appropriate, to differentiate between successful and unsuccessful read operations. In some embodiments, the FPS may also be used to differentiate between disturbed data, which passes an error correction check, and correct data.Type: GrantFiled: October 1, 2012Date of Patent: May 20, 2014Assignee: Apple Inc.Inventors: Matthew J. Byom, Kenneth Herman