Patents by Inventor Matthew J. Craighead

Matthew J. Craighead has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10157061
    Abstract: According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single vector write mask register, and includes a second field whose contents selects the single general purpose register. The source operand is a write mask including a plurality of one bit vector write mask elements that correspond to different multi-bit data element positions within architectural vector registers. The method also includes, responsive to executing the single occurrence of the single instruction, storing data in the single general purpose register such that its contents represent either a first or second scalar constant based on whether the plurality of one bit vector write mask elements in the source operand are all zero.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Jesus Corbal, Matthew J. Craighead, Bret L. Toll, Andrew T. Forsyth
  • Publication number: 20160041827
    Abstract: A method is described that includes fetching an instruction and decoding the instruction. The method further includes fetching a first mask vector from a first mask register space location identified by the instruction. The method further includes fetching a second mask vector from a second mask register space location identified by the instruction. The method also includes executing the instruction by merging the first and second mask vectors into a single data structure and causing the single data structure to be written into a memory location identified by the instruction.
    Type: Application
    Filed: December 23, 2011
    Publication date: February 11, 2016
    Inventors: Jesus Corbal, Matthew J Craighead, Dennis R Bradford, Jonathan C. Hall, Andrew T. Forsyth
  • Patent number: 9069792
    Abstract: A method and system for efficient usage of revision control system resources by providing a client-based file system tree based on managed cache resources is provided. The managed cache resources include both a persistent, disk-based cache that maintains copies of requested file data from a repository server and an ordered tree data structure-based metadata cache for tracking file metadata across revisions. Embodiments of the present invention further maintain in the data cache data related only to specifically requested files. Embodiments of the present invention further track a range of versions of the file system tree for which particular file versions are applicable, so that unnecessary downloading to the client of unchanged files is avoided. Thus, file data and metadata are only requested from a repository server when needed and only a single version of a file is maintained until a modification to that file is made.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: June 30, 2015
    Assignee: Conifer Systems LLC
    Inventor: Matthew J. Craighead
  • Publication number: 20140297991
    Abstract: According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single vector write mask register, and includes a second field whose contents selects the single general purpose register. The source operand is a write mask including a plurality of one bit vector write mask elements that correspond to different multi-bit data element positions within architectural vector registers. The method also includes, responsive to executing the single occurrence of the single instruction, storing data in the single general purpose register such that its contents represent either a first or second scalar constant based on whether the plurality of one bit vector write mask elements in the source operand are all zero.
    Type: Application
    Filed: December 22, 2011
    Publication date: October 2, 2014
    Inventors: Jesus Corbal, Matthew J. Craighead, Bret L. Toll, Andrew T. Forsyth
  • Patent number: 7898549
    Abstract: A graphics processing subsystem defines a bounding area as the portion of the display buffer and other memory buffers occupied by one or more rendered objects. When clearing the memory buffers, only the portions of the buffers corresponding to the bounding area need to be cleared. A graphics pipeline includes a bounding area memory to store bounding area values. The bounding area values are modified during rendering so that each rendered primitive falls within the bounding area values. The graphics processing subsystem clears a portion of the memory buffer in response to a clear command specifying a bounding area. The clear command may include a set of bounding area values defining the bounding area, or alternatively a reference to the bounding area memory. For applications that draw objects in isolation, the bounding area will be smaller than the window, resulting in a decreased time requirement for clearing the memory buffer.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: March 1, 2011
    Assignee: NVIDIA Corporation
    Inventors: Ross A. Cunniff, Matthew J. Craighead
  • Patent number: 7528839
    Abstract: A graphics processing subsystem defines a bounding area as the portion of the display buffer and other memory buffers occupied by one or more rendered objects. When clearing the memory buffers, only the portions of the buffers corresponding to the bounding area need to be cleared. A graphics pipeline includes a bounding area memory to store bounding area values. The bounding area values are modified during rendering so that each rendered primitive falls within the bounding area values. The graphics processing subsystem clears a portion of the memory buffer in response to a clear command specifying a bounding area. The clear command may include a set of bounding area values defining the bounding area, or alternatively a reference to the bounding area memory. For applications that draw objects in isolation, the bounding area will be smaller than the window, resulting in a decreased time requirement for clearing the memory buffer.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: May 5, 2009
    Assignee: Nvidia Corporation
    Inventors: Ross A. Cunniff, Matthew J. Craighead
  • Patent number: 7511717
    Abstract: Hybrid sampling of pixels of an image involves generating shading values at multiple shading sample locations and generating depth values at multiple depth sample locations, with the number of depth sample locations exceeding the number of shading sample locations. Each shading sample location is associated with one or more of the depth sample locations. Generation and filtering of hybrid sampled pixel data can be done within a graphics processing system, transparent to an application that provides image data.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: March 31, 2009
    Assignee: Nvidia Corporation
    Inventors: Rui M. Bastos, Steven E. Molnar, Michael J. M. Toksvig, Matthew J. Craighead
  • Patent number: 7356621
    Abstract: Transferring data between a requesting program and a hardware device. An program requests a pre-allocation of non-pageable memory. The program requests a transfer via a direct memory access (DMA) from the hardware device into the non-pageable memory. The requesting program is notified when the DMA is complete. The requesting program reads the data from the non-pageable memory. A determination may be made whether a range of addresses specified in the DMA request is within the pre-allocated range of non-pageable memory. If the range of addresses is within the pre-allocated non-pageable memory, the data transfer involves fewer transfers between system memory and the CPU than if the range of addresses is outside the pre-allocated non-pageable memory.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: April 8, 2008
    Assignee: Nvidia Corporation
    Inventor: Matthew J. Craighead
  • Patent number: 7081902
    Abstract: A graphics processor performed gamma correction of the coverage values of pixels. In one embodiment, a gamma correction factor is written into a run-time loadable lookup table of the graphics processor. The gamma corrected coverage values may be used in an anti-aliasing process to form smoothed primitives.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: July 25, 2006
    Assignee: NVIDIA Corporation
    Inventors: Franklin C. Crow, John S. Montrym, Matthew J. Craighead
  • Patent number: 6967663
    Abstract: Hybrid sampling of pixels of an image involves generating shading values at multiple shading sample locations and generating depth values at multiple depth sample locations, with the number of depth sample locations exceeding the number of shading sample locations. Each shading sample location is associated with one or more of the depth sample locations. Generation and filtering of hybrid sampled pixel data can be done within a graphics processing system, transparent to an application that provides image data.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: November 22, 2005
    Assignee: NVIDIA Corporation
    Inventors: Rui M. Bastos, Steven E. Molnar, Michael J. M. Toksvig, Matthew J. Craighead