Abstract: A voice quality performance evaluator includes an interface, memory, processing circuitry and may include a network interface. The interface is adapted to couple to a voice transmission path under test. The memory couples to the interface and is adapted to store an original voice sample and a modified voice sample. The processing circuitry couples to the interface and to the memory, retrieves the original voice sample from the memory and transmits the original voice sample to the voice transmission path under test via the interface. The processing circuitry also receives the modified voice sample via the interface from the voice transmission path under test. Finally, the processing circuitry compares the original voice sample to the modified voice sample in the frequency domain to evaluate the performance of the voice transmission path.

Abstract: Instructions in the processor idle loop are used to measure the percentage of time the processor is at idle. The processor idle loop instructions control the processor to alternate a processor data output between output states. The processor data output thus alternates between states whenever the processor is idle, and remains in the same state when the processor is performing useful tasks. A frequency counter or other indicating device responsive to the rate of processor data output state change directly indicates the amount of time the processor is idle relative to the total amount of processing time. Since the change of state, not the state itself, of the data output is detected, it does not matter what state the data output is left in when the processor is interrupted from performing the idle loop instructions.

Abstract: A specialized tone receiver is capable of detecting tones on many different digital signal channels simultaneously. A single memory is used to buffer incoming digital signals. Independent write and read sequencers write samples into and read samples from the buffer memory, respectively. The write sequencer writes all samples corresponding to a given sample time at essentially the same time, while the read sequencer reads out all of the samples corresponding to a given channel of interest in reverse sequential chronological order (i.e., in the opposite order from the order the samples were written) beginning with the most current sample. A priority structure controls access to the buffer memory, with the read sequencer being granted a higher access priority than the write sequencer.