Patents by Inventor Matthew J. Manusharow

Matthew J. Manusharow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electrical interconnect formed through buildup process
    Patent number: 10028394
    Abstract: This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Matthew J Manusharow
  • Electrical interconnect formed through buildup process
    Patent number: 9955589
    Abstract: This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Matthew J Manusharow
  • In situ-built pin-grid arrays for coreless substrates, and methods of making same
    Patent number: 8686566
    Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 1, 2014
    Assignee: Intel Corporation
    Inventors: Mihir K. Roy, Matthew J. Manusharow