Abstract: Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level.

Abstract: A decision feedback equalizer (DFE) and method includes summer circuits to add a dynamic feedback signal representing an h2 tap to a received input and to speculate on an h1 tap. Data slicers receive and sample the outputs of the summer circuits using a clock signal to produce even data bits and odd data bits. First and second multiplexers receive the even data bits and the odd data bits. A first output latch is configured to receive an output of the first multiplexer to provide a select signal for the second multiplexer and to drive the dynamic feedback signal to an even half summer circuit of the summer circuits. A second output latch is configured to receive an output of the second multiplexer to provide a select signal for the first multiplexer and to drive the dynamic feedback signal to an odd half summer circuit of the summer circuits.

Abstract: Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level.

Abstract: A decision feedback equalizer (DFE) and method includes summer circuits to add a dynamic feedback signal representing an h2 tap to a received input and to speculate on an h1 tap. Data slicers receive and sample the outputs of the summer circuits using a clock signal to produce even data bits and odd data bits. First and second multiplexers receive the even data bits and the odd data bits. A first output latch is configured to receive an output of the first multiplexer to provide a select signal for the second multiplexer and to drive the dynamic feedback signal to an even half summer circuit of the summer circuits. A second output latch is configured to receive an output of the second multiplexer to provide a select signal for the first multiplexer and to drive the dynamic feedback signal to an odd half summer circuit of the summer circuits.