Abstract: A method of forming inter-level contacts or vias between metal layers using a tungsten film deposited into the via using non-collimated sputter deposition. The sputter chamber is configured with a pressure of about 1 mTorr to about 10 mTorr with an inert gas flow of at least 25 cm3/min to about 150 cm3/min. Shielding inside the chamber is coated with a material, preferably, aluminum oxide, that promotes adhesion of tungsten to the shielding. An adhesion layer of titanium may be included prior to deposition of the tungsten film. Non-collimated sputter deposition increases the target to substrate distance inside the sputter chamber; reduces the heating effect associated with traditional collimated sputtering; and provides more robust diffusion barriers.

Abstract: A method of reducing the planarization defects produced during the manufacture of semiconductor devices. A sacrificial layer, having defects produced during a interconnection feature planarization step, is removed prior to the formation of subsequent layers to reduce the replication of unwanted defects.

Abstract: A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.

Abstract: A method of forming inter-level contacts or vias between metal layers using a tungsten film deposited into the via using non-collimated sputter deposition. The sputter chamber is configured with a pressure of about 1 mTorr to about 10 mTorr with an inert gas flow of at least at least 25 cm3/min to about 150 cm3/min. Shielding inside the chamber is coated with a material, preferably, aluminum oxide, that promotes adhesion of tungsten to the shielding. An adhesion layer of titanium may be included prior to deposition of the tungsten film. Non-collimated sputter deposition increases the target to substrate distance inside the sputter chamber; reduces the heating effect associated with traditional collimated sputtering; and provides more robust diffusion barriers.

Abstract: A method of forming inter-level contacts or vias between metal layers using a tungsten film deposited into the via using non-collimated sputter deposition. The sputter chamber is configured with a pressure of about 1 mTorr to about 10 mTorr with an inert gas flow of at least at least 25 cm3/min to about 150 cm3/min. Shielding inside the chamber is coated with a material, preferably, aluminum oxide, that promotes adhesion of tungsten to the shielding. An adhesion layer of titanium may be included prior to deposition of the tungsten film. Non-collimated sputter deposition increases the target to substrate distance inside the sputter chamber; reduces the heating effect associated with traditional collimated sputtering; and provides more robust diffusion barriers.

Abstract: Disclosed is a method and apparatus for polishing a semiconductor wafer. This invention describes a novel in situ method for eliminating residual slurry and slurry abrasive particles on the wafer. A reactant is added to the slurry during the end of the Chemical Mechanical Polish (CMP) process to dissolve the slurry and etch the abrasive particles.

Abstract: A method and apparatus for Chemical-Mechanical Polishing of semiconductor wafers using various formulations of high viscosity slurry.

Abstract: Electrically conductive studs are employed to interconnect bulk active devices and SOI devices in a semiconductor device. Also provided is a method for fabricating such devices.

Abstract: A precision analog metal-metal capacitor is fabricated by forming a first capacitor plate in an insulation layer by forming a trench therein, depositing metal within the trench and planarizing the device. A thin dielectric layer is then deposited and patterned over the first capacitor plate. A second insulator is then deposited over the device and discrete openings etched therein to expose the insulation layer and first metal plate. Metal is deposited within the openings and planarized, thereby forming a contact to the first metal plate and the second metal plate of the capacitor.

Abstract: A polishing pad and method of polishing with a chemical mechanical planarization apparatus includes providing a bulk polishing pad material having a front polishing surface side and a back side. The polishing pad further includes a polishing pad wear indicator for indicating a polishing pad wear during a life cycle of the polishing pad. The polishing pad wear indicator is formed on the back side of the bulk polishing pad material.

Abstract: Disclosed is a method and apparatus for polishing a semiconductor wafer. This invention describes a novel in situ method for eliminating residual slurry and slurry abrasive particles on the wafer. A reactant is added to the slurry during the end of the Chemical Mechanical Polish (CMP) process to dissolve the slurry and etch the abrasive particles.

Abstract: Electrically conductive studs are employed to interconnect bulk active devices and SOI devices in a semiconductor device. Also provided is a method for fabricating such devices.

Abstract: A gas discharge illumination device is prepared by encapsulating ionizable gas within microporous or nanoscale sealed cavities created within a matrix material. Upon exposure of said matrix material to an electric field, the ionizable gas becomes ionized and emits light. By incorporating several different ionizable gases into one matrix material, a display with different colors of light can be produced. The gas discharge illumination device can be fabricated by a variety of techniques including selective cavity formation with overcoating taking place in an ionizable gas ambient, and bubbling ionizable gas through the matrix material while it is in viscous form. The gas discharge illumination device can be used to form either active or passive displays, as a sensor for detecting electric fields, and in other applications.

Abstract: A precision analog metal-metal capacitor is fabricated by forming a first capacitor plate in an insulation layer by forming a trench therein, depositing metal within the trench and planarizing the device. A thin dielectric layer is then deposited and patterned over the first capacitor plate. A second insulator is then deposited over the device and discrete openings etched therein to expose the insulation layer and first metal plate. Metal is deposited within the openings and planarized, thereby forming a contact to the first metal plate and the second metal plate of the capacitor.

Abstract: The invention provides an interconnect line which comprises a metallization layer and a plurality of transverse diffusion barriers spaced within said metallization layer. The transverse diffusion barriers separate the length of metallization of the line into discrete sections, such that each section is only 20-50 microns in length. The diffusion barriers reduce electromigration and metal creep within the metal line, each of which can cause failure of the line. The invention further provides such an interconnect line formed within an insulator layer, for use in multi-level interconnect structures.

Abstract: A chemical mechanical planarization tool and method are presented employing a non-linear motion of the carrier arm relative to the polishing pad. The non-linear motion of the carrier arm relative to the polishing pad can be accomplished in a variety of ways, for example, employing a mechanical template having an irregular opening or programming the carrier displacement mechanism to move the carrier in an irregular, non-rotational X-Y path over the polishing pad.

Abstract: Bidirectional field emission devices (FEDs) and associated fabrication methods are described. A basic device includes a first unitary field emission structure and an adjacently positioned, second unitary field emission structure. The first unitary structure has a first cathode portion and a first anode portion, while the second unitary structure has a second cathode portion and a second anode portion. The structures are positioned such that the first cathode portion opposes the second anode portion so that electrons may flow by field emission thereto and the second cathode portion opposes the first anode portion, again so that electrons may flow by field emission thereto. A control mechanism defines whether the device is active, while biasing voltages applied to the first and second unitary structures define the direction of current flow. Multiple applications exist for such a bidirectional FED. For example, an FED DRAM cell is discussed, as are methods for fabricating the various devices.

Abstract: An interconnect line is formed of a metallization layer and a plurality of transverse diffusion barriers spaced within said metallization layer. The transverse diffusion barriers separate the length of metallization of the line into discrete sections, such that each section is only 20-50 microns in length. The diffusion barriers reduce electromigration and metal creep within the metal line, each of which can cause failure of the line. The method further provides such an interconnect line formed within an insulator layer, for use in multi-level interconnect structures.

Abstract: Bidirectional field emission devices (FEDs) and associated fabrication methods are described. A basic device includes a first unitary field emission structure and an adjacently positioned, second unitary field emission structure. The first unitary structure has a first cathode portion and a first anode portion, while the second unitary structure has a second cathode portion and a second anode portion. The structures are positioned such that the first cathode portion opposes the second anode portion so that electrons may flow by field emission thereto and the second cathode portion opposes the first anode portion, again so that electrons may flow by field emission thereto. A control mechanism defines whether the device is active, while biasing voltages applied to the first and second unitary structures define the direction of current flow. Multiple applications exist for such a bidirectional FED. For example, an FED DRAM cell is discussed, as are methods for fabricating the various devices.