Patents by Inventor Matthew J. Schade

Matthew J. Schade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware performance monitor (HPM) with extended resolution for adaptive voltage scaling (AVS) systems
    Patent number: 8572426
    Abstract: An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: October 29, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Wai Cheong Chan, Matthew J. Schade
  • Hardware performance monitor (HPM) with extended resolution for adaptive voltage scaling (AVS) systems
    Publication number: 20110291729
    Abstract: An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wai Cheong Chan, Matthew J. Schade