Abstract: A system and method for analyzing the timing requirements of a memory array are disclosed. The memory cell circuitry used in the original memory array may utilize two bi-directional passgate transistors which are both used during read and write operations on the memory cell, e.g., where signals can flow across the passgate transistors in two directions. A model of the memory array may be created according to a memory cell model that uses uni-directional passgate transistors. Modeling the memory array with uni-directional circuitry may enable a static timing analysis tool to determine the critical path through the memory array. Once the critical path has been determined from the model of the memory array, a dynamic simulation of the critical path in the original memory array may be performed to accurately determine the timing requirements of the original memory array.

Abstract: In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation of the circuit (e.g. a netlist), replacing the identified transistors with aged transistors (e.g. by modifying parameters of the transistors in the netlist). The aging analysis tool may process the modified netlist over a range of conditions at which the circuit is expected to operate, to ensure that the design meets specifications after aging. The process may be repeated until the aged design meets specifications (with circuit modifications made by the designer to improve the design).