Abstract: A power tool with a combined printed circuit board (PCB) that reduces internal wiring of the power tool and provides a large amount of air flow to internal components. In some instances, the combined PCB has a surfboard shape and includes a motor control unit and power switching elements (Field Effect Transistors or FETs). The combined surfboard PCB is located above the trigger, but below the motor and drive mechanism. In other instances, the combined PCB has a doughnut shape and is located coaxially with a motor shaft. The combined PCB may be positioned between a doughnut-shaped control PCB and the motor.

Abstract: A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer (24, FIG. 2) between an application layer (22) and a physical layer (26) which identifies the input and output pins for the engine and their functions.

Abstract: An optical data processing network having an optical network interface is disclosed. The optical data processing network includes a first multi-processor system and a second multi-processor system. The first multi-processor system includes a first set of processors and a first set of optical network interfaces electrically coupled to the first set of processors. Similarly, the second multi-processor system includes a second set of processors and a second set of optical network interfaces electrically coupled to the second set of processors. An optical cable is connected between the first set and the second set of optical network interfaces. The first multi-processor system communicates with the second multi-processor system via the optical cable.

Abstract: An optical data processing network having an optical network interface is disclosed. The optical data processing network includes a first multi-processor system and a second multi-processor system. The first multi-processor system includes a first set of processors and a first set of optical network interfaces electrically coupled to the first set of processors. Similarly, the second multi-processor system includes a second set of processors and a second set of optical network interfaces electrically coupled to the second set of processors. An optical cable is connected between the first set and the second set of optical network interfaces. The first multi-processor system communicates with the second multi-processor system via the optical cable.

Abstract: A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer (24, FIG. 2) between an application layer (22) and a physical layer (26) which identifies the input and output pins for the engine and their functions.

Abstract: In a communications or jamming system, accurate timing of the transmission of digitally processed signals is accomplished through the use of standard off-the-shelf components. In order to eliminate the need for high-cost, difficult to develop, specific digital hardware or realtime synchronous software not available from the standard off-the-shelf components, the output from the non-real time components is coupled to a realtime interface that assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components. In one embodiment, the signals to be transmitted are digitized and then packetized, with the data to be transmitted reconstructed using non-real time digital processing.

Abstract: A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer (24, FIG. 2) between an application layer (22) and a physical layer (26) which identifies the input and output pins for the engine and their functions.

Abstract: In a communications or jamming system, accurate timing of the transmission of digitally processed signals is accomplished through the use of standard off-the-shelf components. In order to eliminate the need for high-cost, difficult to develop, specific digital hardware or realtime synchronous software not available from the standard off-the-shelf components, the output from the non-real time components is coupled to a realtime interface that assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components. In one embodiment, the signals to be transmitted are digitized and then packetized, with the data to be transmitted reconstructed using non-real time digital processing.

Abstract: In a communications or jamming system, accurate timing for the control of the frequency, amplitude, modulation type, pulse repetition rate or other transmit characteristics is achieved for the transmission of digitally processed packetized signals through the use of standard non-realtime off-the-shelf components for the digital processing and a realtime interface which reads transmit chain headers and, with the assistance of a precise time reference, assures that the transmit chain is configured in time to transmit the packets. Note that the realtime interface assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components used in upstream digital processing.

Abstract: An optical data processing network having an optical network interface is disclosed. The optical data processing network includes a first multi-processor system and a second multi-processor system. The first multi-processor system includes a first set of processors and a first set of optical network interfaces electrically coupled to the first set of processors. Similarly, the second multi-processor system includes a second set of processors and a second set of optical network interfaces electrically coupled to the second set of processors. An optical cable is connected between the first set and the second set of optical network interfaces. The first multi-processor system communicates with the second multi-processor system via the optical cable.

Abstract: An optical data processing network having an optical network interface is disclosed. The optical data processing network includes a first multi-processor system and a second multi-processor system. The first multi-processor system includes a first set of processors and a first set of optical network interfaces electrically coupled to the first set of processors. Similarly, the second multi-processor system includes a second set of processors and a second set of optical network interfaces electrically coupled to the second set of processors. An optical cable is connected between the first set and the second set of optical network interfaces. The first multi-processor system communicates with the second multi-processor system via the optical cable.

Abstract: A layered mechanism for integrating programmable devices into software based frameworks for distributed processing wherein the software framework interfaces with an adaptation layer, which in turn interfaces with a programmable device, such as a field programmable gate array (FPGA).

Abstract: In a communications or jamming system, accurate timing of the transmission of digitally processed signals is accomplished through the use of standard off-the-shelf components. In order to eliminate the need for high-cost, difficult to develop, specific digital hardware or realtime synchronous software not available from the standard off-the-shelf components, the output from the non-real time components is coupled to a realtime interface that assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components. In one embodiment, the signals to be transmitted are digitized and then packetized, with the data to be transmitted reconstructed using non-real time digital processing.

Abstract: In a communications or jamming system, accurate timing for the control of the frequency, amplitude, modulation type, pulse repetition rate or other transmit characteristics is achieved for the transmission of digitally processed packetized signals through the use of standard non-realtime off-the-shelf components for the digital processing and a realtime interface which reads transmit chain headers and, with the assistance of a precise time reference, assures that the transmit chain is configured in time to transmit the packets. Note that the realtime interface assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components used in upstream digital processing.