Abstract: Embodiments herein describe a glitch detector circuit (and method of operation) for detecting glitches in a clock signal. In one embodiment, the glitch detector includes a shift register that samples the reference clock using a clock signal output by a PLL. The value in a first memory element of the shift register can be sampled to previous values that were stored (and then bit shifted) in the shift register. If there is a mismatch, the glitch detector indicates there was a clock glitch in the reference clock, and a corrective action can be performed.

Abstract: Embodiments herein describe circuitry and techniques to implement an enhanced PPM frequency offset detector and methods for implementing operational functions of one or more embodiments of the PPM frequency offset detector to detect a frequency offset between two clock signals. An enhanced PPM frequency offset detector of one or more embodiments reduces circuitry and power requirements, eliminating circuitry requirements of a third reference clock signal to detect the frequency offset of some traditional arrangements, and effectively and efficiently detects a PPM frequency offset between two clock signals.

Abstract: Embodiments herein describe a glitch detector circuit (and method of operation) for detecting glitches in a clock signal. In one embodiment, the glitch detector includes a shift register that samples the reference clock using a clock signal output by a PLL. The value in a first memory element of the shift register can be sampled to previous values that were stored (and then bit shifted) in the shift register. If there is a mismatch, the glitch detector indicates there was a clock glitch in the reference clock, and a corrective action can be performed.

Abstract: Embodiments herein describe circuitry and techniques to implement an enhanced PPM frequency offset detector and methods for implementing operational functions of one or more embodiments of the PPM frequency offset detector to detect a frequency offset between two clock signals. An enhanced PPM frequency offset detector of one or more embodiments reduces circuitry and power requirements, eliminating circuitry requirements of a third reference clock signal to detect the frequency offset of some traditional arrangements, and effectively and efficiently detects a PPM frequency offset between two clock signals.

Abstract: A deskew circuit receives a data signal and a clock signal of differing frequencies and indeterminate phase relationship. The deskew circuit selectively applies a delay to a data signal to obtain a delayed data signal. First and second latches of the deskew circuit latch the delayed data signal based on a rising edge and a falling edge of the clock signal, respectively. The deskew circuit detects a phase difference between output signals of the first and second latches. The deskew circuit adjusts the delay applied to the data signal based on the detected phase difference.

Abstract: A deskew circuit receives a data signal and a clock signal of differing frequencies and indeterminate phase relationship. The deskew circuit selectively applies a delay to a data signal to obtain a delayed data signal. First and second latches of the deskew circuit latch the delayed data signal based on a rising edge and a falling edge of the clock signal, respectively. The deskew circuit detects a phase difference between output signals of the first and second latches. The deskew circuit adjusts the delay applied to the data signal based on the detected phase difference.

Abstract: A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.

Abstract: A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.

Abstract: A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).

Abstract: A circuit and method for implementing variable threshold voltage transistors in a complementary metal oxide semiconductor (CMOS) semiconductor chip, and a design structure on which the subject circuit resides are provided. Variable threshold voltage transistors are provided utilizing the NWELL and PWELL proximity effects of the CMOS semiconductor chip without any additional mask steps. A distance between an adjacent field effect transistor (FET) and an NWELL edge or PWELL edge is adjusted to selectively provide a needed threshold voltage for the FET.

Abstract: The invention relates to a feedback loop for a laser diode driving circuit for ensuring that the laser diode generates optical power at a constant safe level. The feedback loop includes a monitor diode, which generates a monitor current Imon, and a set resistance for generating a set voltage based on the monitor current and the set resistance. The set voltage is compared with a reference voltage in an operational amplifier, which generates a control signal for controlling the laser diode current source. The laser diode current source dictates the amount of bias current transmitted to the laser diode. Safety features, in the form of voltage comparators, are provided to ensure that: a) the feedback loop is closed, i.e. Imon is not too low; b) the optical power is not above standard safety threshold, i.e. Imon is not too high; and c) the monitor diode voltage is sufficient to provide specified optical power to electrical power conversion.

Abstract: An on-chip parallel data generator, including a Built In Self Test (BIST) generator, is integrated into a laser driver array of a parallel optical communication transmitter so that all optical outputs switch simultaneously. The BIST generator requires only one clock input which clocks the BIST generator for all channels. The optical outputs respond to either the on-chip BIST generator or the electrical inputs if a valid signal is present on the inputs.

Abstract: A method and apparatus are provided to ensure that laser optical power does not exceed a “safe” level in a DC coupled open loop parallel optical link in the event that a fiber optic ribbon cable is broken or otherwise severed. A duplex parallel optical link includes a transmitter and receiver pair and a fiber optic ribbon that includes a designated number N of channels that cannot be split. The duplex transceiver includes a corresponding transmitter and receiver that are physically attached to each other and cannot be detached therefrom, so as to ensure safe, laser optical power in the event that the fiber optic ribbon cable is broken or severed. Safe optical power is ensured by redundant current and voltage safety checks, and the corresponding low duty cycle signal is generated by a safety pulse generator in the safety channel.

Abstract: The invention relates to a feedback loop for a laser diode driving circuit for ensuring that the laser diode generates optical power at a constant safe level. The feedback loop includes a monitor diode, which generates a monitor current Imon, and a set resistance for generating a set voltage based on the monitor current and the set resistance. The set voltage is compared with a reference voltage in an operational amplifier, which generates a control signal for controlling the laser diode current source. The laser diode current source dictates the amount of bias current transmitted to the laser diode. Safety features, in the form of voltage comparators, are provided to ensure that: a) the feedback loop is closed, i.e. Imon is not too low; b) the optical power is not above standard safety threshold, i.e. Imon is not too high; and c) the monitor diode voltage is sufficient to provide specified optical power to electrical power conversion.

Abstract: A method and apparatus are provided to ensure that laser optical power does not exceed a “safe” level in an open loop parallel optical link in the event that a fiber optic ribbon cable is broken or otherwise severed. A duplex parallel optical link includes a transmitter and receiver pair and a fiber optic ribbon that includes a designated number of channels that cannot be split. The duplex transceiver includes a corresponding transmitter and receiver that are physically attached to each other and cannot be detached therefrom, so as to ensure safe, laser optical power in the event that the fiber optic ribbon cable is broken or severed. Safe optical power is ensured by redundant current and voltage safety checks.

Abstract: Optical power adjustment is provided for parallel optical transmitters, in particular, for an array of vertical cavity surface emitting lasers (VCSEL's). The lasers in the array can be independently digitally adjusted with associated digital circuitry to compensate for manufacturing and temperature variations. In particular, the threshold current and modulation current for each VCSEL in the array, as well as a global temperature coefficient for all the VCSEL's in the array, can be digitally setup and adjusted for desired power levels. Once set, the associated digital code can be stored in non-volatile memory, and loaded at powering-up of the transmitters.

Abstract: A laser driver, e.g., a vertical cavity surface emitting laser (VCSEL) driver, with low duty cycle distortion is provided. An fT doubler circuit, used as the driver input, has two current sources, and reduces parasitic capacitance which can cause duty cycle distortion. The current sources may be analog or digital sources, the latter being digitally adjustable to provide for digital modulation adjustment. A current mirror circuit with a reference current source is provided for the two current sources.

Abstract: A method and apparatus are provided to ensure that laser optical power does not exceed a “safe” level in a DC coupled open loop parallel optical link in the event that a fiber optic ribbon cable is broken or otherwise severed. A duplex parallel optical link includes a transmitter and receiver pair and a fiber optic ribbon that includes a designated number N of channels that cannot be split. The duplex transceiver includes a corresponding transmitter and receiver that are physically attached to each other and cannot be detached therefrom, so as to ensure safe, laser optical power in the event that the fiber optic ribbon cable is broken or severed. Safe optical power is ensured by redundant current and voltage safety checks, and the corresponding low duty cycle signal is generated by a safety pulse generator in the safety channel.

Abstract: A selectable receiver includes a first receiver module for receiving first input signal type and a second receiver module, different from the first receiver module, for receiving a second input signal type, both receiver modules coupled to the same receiver inputs. An internal common mode voltage for the first signal type or for the second signal type, is provided by respective common mode voltage networks, to the first or to the second receiver module, to facilitate AC coupling with the appropriate DC common mode voltage required by the signal type. If direct coupled, the internal common mode voltage is effectively swamped out by the common mode voltage of the input signal. The first receiver module or the second receiver module, and the associated first common mode voltage or second common mode voltage, are selected in the receiver based on a control signal.

Abstract: The constant current source circuit provides current that compensates for changes in performance resulting from changes of temperature. The circuit mixes variable amounts of current having a negative temperature coefficient with current having a positive temperature coefficient. Analog and digital embodiments of the circuit are disclosed. In the analog embodiment, the amount of current having a positive temperature coefficient is added to an amount of current having a negative temperature coefficient as determined by the voltage difference between a variable control voltage input to transistors and a bandgap reference voltage.