Abstract: Techniques to operate a time division multiplexing (TDM) media access control (MAC) module include examples of facilitating use of shared resources allocated to ports of a network interface based on a time slot mechanism. The shared resources allocated to process packet data received or sent through the ports of the network interface.

Abstract: Multi-port Media Control Channel (MAC) with flexible data-path width. A multi-port receive (RX) MAC block includes multiple RX ports and a plurality of RX circuit blocks comprising an RX MAC pipeline for performing MAC Layer operations on RX data received at the RX ports. The RX circuit blocks are connected with variable-width datapath segments, and the RX MAC block is configured to implement a multi-port arbitration scheme such as a TDM (Time-Division Multiplexed) scheme under which RX data received at a given RX port are forwarded over the variable-width datapath segments using datapath widths associated with that RX port. A multi-port transmit (TX) MAC block implementing a TX MAC pipeline comprising TX circuit blocks connected with variable-width datapath segments is also provided. The RX and TX MAC blocks include CRC modules configured to calculate CRC values on input data received over datapaths having different widths.

Abstract: Particular embodiments described herein provide for an electronic device that includes at least one processor operating at eight hundred (800) megahertz and can be configured to receive a data stream, parse packets in the data stream, and process at least two (2) full packets from the data stream in a single clock cycle. In an example, the data stream is at least a two hundred (200) gigabit Ethernet data stream and a bus width is at least thirty-two (32) bytes.

Abstract: Techniques to operate a time division multiplexing (TDM) media access control (MAC) module include examples of facilitating use of shared resources allocated to ports of a network interface based on a time slot mechanism. The shared resources allocated to process packet data received or sent through the ports of the network interface.

Abstract: A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.

Abstract: Received undersized Ethernet frames are isolated and discarded in a Media Access Control (MAC) sublayer having a bus width greater than the number of bytes in a received minimum size Ethernet frame. The MAC sublayer maintains one counter to track the total number of undersized frames (undersized frames with good Cyclic Redundancy Check (CRC)) and runts with bad CRC). Undersized Ethernet frames are discarded by the MAC sublayer prior to calculating Cyclic Redundancy Check (CRC) for the Ethernet Frame.

Abstract: Particular embodiments described herein provide for an electronic device that includes at least one processor operating at eight hundred (800) megahertz and can be configured to receive a data stream, parse packets in the data stream, and process at least two (2) full packets from the data stream in a single clock cycle. In an example, the data stream is at least a two hundred (200) gigabit Ethernet data stream and a bus width is at least thirty-two (32) bytes.

Abstract: A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states.