Abstract: A data processing system comprising a transpose system configured to receive video ordered pixel data and to generate bit plane blocks of data. A write buffer configured to receive the bit plane blocks of data and to generate bit plane data frames. A memory controller configured to receive the bit plane data frames and to write a first bit plane data frame to a memory while simultaneously reading a second bit plane data frame from memory. A read buffer configured to receive the second bit plane data frame and to convert the second bit plane data frame to a digital display device format.

Abstract: A data processing system comprising a transpose system configured to receive video ordered pixel data and to generate bit plane blocks of data. A write buffer configured to receive the bit plane blocks of data and to generate bit plane data frames. A memory controller configured to receive the bit plane data frames and to write a first bit plane data frame to a memory while simultaneously reading a second bit plane data frame from memory. A read buffer configured to receive the second bit plane data frame and to convert the second bit plane data frame to a digital display device format.

Abstract: In accordance with the teachings of the present invention, a system and method for bit stream compatible local link encryption are provided. In particular embodiments of the present invention, the method includes generating a random number stream using an active line count of a frame of video as an input to a first random number generator in a playback server; encrypting data at the playback server based upon a first deterministic mapping between the first random number stream and the data, wherein the first deterministic mapping prevents the generation of prohibited codes; transporting the encrypted data from the playback server to a digital video projector; generating a second random number stream using the active line count of the frame of video as an input to a second random number generator in the digital video projector; and decrypting the encrypted data at the digital video projector based upon a second deterministic mapping between the second random number stream and the encrypted data.

Abstract: In accordance with the teachings of the present invention, a system and method for transporting an ancillary data packet in the active area of a video stream are provided. In particular embodiments of the present invention, the method includes coupling a playback server and a digital video projector with a DVI link; placing an ancillary data packet of link encryption metadata in a false line of video in an active area of a frame of video at the playback server, a remainder of the active area comprising true lines of video; transmitting the ancillary data packet from the playback server to a digital video projector through the DVI link; extracting the ancillary data packet from the frame of video at the digital video projector; and displaying the remainder of the active area of the frame of video at the digital video projector.

Abstract: A method and apparatus for a signal encryption device constructed to perform synchronous stream cipher encryption for a sequence of input words with restricted codes. The encryption device includes a keystream generator for producing a sequence of pseudorandom words from a key, and an adder that is used to sum the output of the keystream generator and the input words. A lookup table of size substantially twice the number of possible input words provides encrypted codes excluding restricted codes from the summed signal. A signal encryption and decryption system is constructed by including a second keystream generator for producing a second sequence of pseudorandom words from the key, and a second adder to produce a second summed signal from the output of the second keystream generator and the encrypted codes. A corresponding lookup table provides decrypted codes excluding restricted codes from the second summed signal.

Abstract: A method of producing an image. Image data word comprising image data bits for a portion of the image is received at a first frame rate. At least two threshold data values are selected. A first portion of the image data word is compared with the threshold data values. A second portion of said image data word is displayed at a frame rate at least two times said first frame rate. Image data based on the comparison between the first portion of the image data word and the threshold data values is displayed at a frame rate at least two times the first frame rate.

Abstract: A method and system for displaying fractional bit data in order to increase the bit depth of a PWM display without requiring the use of an excessive number of bit planes. One embodiment of the present invention combines the outputs of two random number generators (702) with the outputs of a row counter (704) and column counter (706) to yield row and column indexes into two 32×32 cell blue noise masks. The row and column indexes select a blue noise mask threshold for a given pixel. The threshold from the first blue noise mask (708) is applied to a comparator (710) where it is compared to the fractional bit portion of the pixel data. A first blue noise bit, BN(1), is generated based on this comparison. Typically, BN(1) is a “1” when the fractional portion of the pixel data exceeds the threshold value from the mask. The same threshold data is also processed by inverter (712) to produce the threshold that would be shored in an inverted form of Mask A.

Abstract: A method and system for displaying fractional bit data in order to increase the bit depth of a PWM display without requiring the use of an excessive number of bit planes. One embodiment of the present invention combines the outputs of two random number generators (702) with the outputs of a row counter (704) and column counter (706) to yield row and column indexes into two 32×32 cell blue noise masks. The row and column indexes select a blue noise mask threshold for a given pixel. The threshold from the first blue noise mask (708) is applied to a comparator (710) where it is compared to the fractional bit portion of the pixel data. A first blue noise bit, BN(1), is generated based on this comparison. Typically, BN(1) is a “1” when the fractional portion of the pixel data exceeds the threshold value from the mask. The same threshold data is also processed by inverter (712) to produce the threshold that would be shored in an inverted form of Mask A.

Abstract: A display and control module sends synchronization signals and camera display codes to a loop multiplexer module and a home run multiplexer module. The loop multiplexer module has a plurality of cameras coupled to a loop multiplexer unit. The loop multiplexer unit controls the synchronization and selection of video from the cameras for sending to the display and control module. The home run multiplexer includes a home run multiplexer unit coupled to a plurality of coaxial cables, each coaxial cable having at least one video camera thereon. The home run multiplexer unit receives the synchronization and control signals from the display and control module and uses those signals for synchronizing and selecting video images from one of the plurality of cameras for sending to the display and control module. The display and control module uses the video signals from the loop multiplexer module and the home run multiplexer module to display on a display.

Abstract: A system for processing video signals to compensate for distance-induced video signal delays includes a camera controller and distant camera are arranged so that the camera controller generates and sends a synchronization signal to the camera, which upon receiving it generates and sends back to the camera controller a reference signal starting at a fixed time following camera receipt of the synchronization signal, and further arranged so that the reference signal upon receipt by the camera controller is compared by the reference pulse comparator to determine if it is late, early, or at an acceptable time, upon which determination a phase adjustment signal is generated and sent by the camera controller to the camera second timing generator phase offset adjustment section to adjust appropriately the timing of the insertion of a video signal onto the transmission line by the camera.

Abstract: A video signal routing system includes a video signal carrying line arranged in a loop beginning and ending at a signal multiplexer, a plurality of video cameras electrically connected to the line at points spaced therealong, and a video output line connected to receive video signals from the multiplexer. A synchronization signal insertion device and a code signal insertion device are located in the video signal carrying line adjacent the beginning of the loop between the multiplexer and the cameras. A duplicate synchronization signal insertion device and a duplicate code signal insertion device are located in the video signal carrying line adjacent the end of the loop between the multiplexer and the cameras. A timing generator and interface receives signals from a synch detector and a video level detector in the video output line and is controlled by a microcontroller.