Patents by Inventor Matthew John Sherbin
Matthew John Sherbin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055313Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.Type: ApplicationFiled: October 25, 2023Publication date: February 15, 2024Inventors: Michael Todd Wyant, Matthew John Sherbin, Christopher Daniel Manack, Patrick Francis Thompson, You Chye How
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Patent number: 11837518Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.Type: GrantFiled: August 26, 2020Date of Patent: December 5, 2023Assignee: Texas Instruments IncorporatedInventors: Michael Todd Wyant, Matthew John Sherbin, Christopher Daniel Manack, Patrick Francis Thompson, You Chye How
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Publication number: 20230260839Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, CHRISTOPHER DANIEL MANACK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO, MING ZHU, JOSEPH O. LIU
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Patent number: 11664276Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.Type: GrantFiled: November 30, 2018Date of Patent: May 30, 2023Assignee: Texas Instruments IncorporatedInventors: Matthew John Sherbin, Michael Todd Wyant, Christopher Daniel Manack, Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Ming Zhu, Joseph O. Liu
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Publication number: 20230040267Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.Type: ApplicationFiled: October 5, 2022Publication date: February 9, 2023Inventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Patent number: 11482442Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.Type: GrantFiled: February 24, 2021Date of Patent: October 25, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Patent number: 11469141Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.Type: GrantFiled: August 7, 2018Date of Patent: October 11, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Publication number: 20220068744Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.Type: ApplicationFiled: August 26, 2020Publication date: March 3, 2022Inventors: Michael Todd WYANT, Matthew John SHERBIN, Christopher Daniel MANACK, Patrick Francis THOMPSON, You Chye HOW
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Patent number: 11171031Abstract: A die matrix expander includes a subring including ?3 pieces, and a wafer frame supporting a dicing tape having an indentation for receiving pieces of the subring. The subring prior to expansion sits below a level of the wafer frame and has an outer diameter <an inner diameter of the wafer frame. A translation guide coupled to the subring driven by mechanical force applier moves the subring pieces in an angled path upwards and outwards for stretching the dicing tape including to a top most stretched position above the wafer frame that is over or outside the wafer frame. A cap placed on the pieces of the subring after being fully expanded over the dicing tape locks the dicing tape in the top most stretched position and secures the pieces of the expanded subring in place including when within the indentation during an additional expansion during a subsequent die pick operation.Type: GrantFiled: July 23, 2018Date of Patent: November 9, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Hiroyuki Sada, Shoichi Iriguchi, Genki Yano
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Publication number: 20210210440Abstract: An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.Type: ApplicationFiled: January 8, 2020Publication date: July 8, 2021Inventors: Christopher Daniel Manack, Qiao Chen, Michael Todd Wyant, Matthew John Sherbin, Patrick Francis Thompson
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Publication number: 20210183683Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.Type: ApplicationFiled: February 24, 2021Publication date: June 17, 2021Inventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Publication number: 20200176314Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, CHRISTOPHER DANIEL MANACK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO, MING ZHU, JOSEPH O. LIU
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Publication number: 20200075386Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.Type: ApplicationFiled: August 30, 2018Publication date: March 5, 2020Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, DAVE CHARLES STEPNIAK, SADA HIROYUKI, SHOICHI IRIGUCHI, GENKI YANO
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Publication number: 20200051860Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.Type: ApplicationFiled: August 7, 2018Publication date: February 13, 2020Inventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Publication number: 20200035833Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.Type: ApplicationFiled: October 1, 2019Publication date: January 30, 2020Inventors: Steven Kummerl, Matthew John Sherbin, Saumya Gandhi
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Publication number: 20200027772Abstract: A die matrix expander includes a subring including ?3 pieces, and a wafer frame supporting a dicing tape having an indentation for receiving pieces of the subring. The subring prior to expansion sits below a level of the wafer frame and has an outer diameter <an inner diameter of the wafer frame. A translation guide coupled to the subring driven by mechanical force applier moves the subring pieces in an angled path upwards and outwards for stretching the dicing tape including to a top most stretched position above the wafer frame that is over or outside the wafer frame. A cap placed on the pieces of the subring after being fully expanded over the dicing tape locks the dicing tape in the top most stretched position and secures the pieces of the expanded subring in place including when within the indentation during an additional expansion during a subsequent die pick operation.Type: ApplicationFiled: July 23, 2018Publication date: January 23, 2020Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, DAVE CHARLES STEPNIAK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO
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Patent number: 10431684Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.Type: GrantFiled: April 22, 2016Date of Patent: October 1, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Kummerl, Matthew John Sherbin, Saumya Gandhi
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Publication number: 20170309748Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.Type: ApplicationFiled: April 22, 2016Publication date: October 26, 2017Inventors: Steven Kummerl, Matthew John Sherbin, Saumya Gandhi