Abstract: A processor system is disclosed wherein said processor system is adapted to communicate over at least one one-wire network utilizing one-wire communications protocol. For the embodiment of the invention in which the processor system acts as a network master, the processor system includes a master UART especially configured to control communications over such network according to one-wire protocol. For the embodiment of the invention in which the processor communicates over two one-wire networks, the processor system includes a first UART which acts as a slave and a second UART which acts as a master.

Abstract: A hardware circuit for verifying the execution of software is disclosed wherein the circuit compares a stored value with another value that is stored at at least one predetermined time in the course of program execution. If the two values correspond in some predetermined fashion then it is verified with a level of certainty that the program executed the program steps at or near the predetermined times.

Abstract: Interrupt circuitry for a processor comprises a plurality of interrupt inputs, an interrupt output, combinatorial logic with a plurality of combinatorial logic inputs connected to the plurality of interrupt inputs and with a combinatorial logic output connected to the interrupt output wherein an interrupt output signal at the interrupt output is a function of interrupt signals at the plurality of interrupt inputs; and an interrupt mode select connected to the combinatorial logic wherein an interrupt mode select signal from the interrupt mode select controls the function. The interrupt mode select signal from the interrupt mode select selects the function to be either AND or OR.

Abstract: A clock monitor circuit which is frequency-independent. The crystal terminals on a circuit being monitored for activity may be considered as an inverter combined with a phase delay. The innovative circuit has clock-output and clock-input terminals which are connected to the clock terminals on the circuit being monitored. When a rising edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be high. Similarly, when a falling edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be low. Whenever a low level is detected on a rising edge, or a high level on a falling edge, a counter chain will start counting down. The counter chain will be reset only when a high level is detected on a rising edge AND a low level is detected on the next falling edge.

Abstract: An adjunct chip, usable as a peripheral to a microprocessor, which detects power failure, and which puts the microprocessor into a known state upon power down. In order to reliably and stably put the microprocessor into a known state, several clocks are generated after the reset signal. However, since the power supply is falling, it is possible that the crystal-controlled oscillator may already have become unreliable. Therefore, a simple logic circuit (a ring oscillator, in the presently preferred embodiment) is used to generate the needed additional clocks at power-down. The switch from crystal-controlled oscillator to ring oscillator is stabilized by using a latched multiplexer to switch between the two oscillator inputs. The latch adds hysteresis to the switching characteristic, avoiding any problems of switching jitter.