Patents by Inventor Matthew Kaufmann
Matthew Kaufmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11911288Abstract: An embodiment includes an orthopedic fusion system comprising: a cage; a curved first channel coupling a lateral wall of the cage to a superior surface of the cage; a curved second channel coupling the lateral wall of the cage to an inferior surface of the cage; a third channel coupling the superior surface of the cage to the inferior surface of the cage; a curved first anchor configured to slide within the first channel; a curved second anchor configured to slide within the second channel; and a resilient member comprising a resilient first arm that projects across a portion of the first channel and a resilient second arm that projects across a portion of the second channel. Other embodiments are described herein.Type: GrantFiled: May 17, 2021Date of Patent: February 27, 2024Assignee: Genesys SpineInventors: Joshua Kaufmann, Greg Calbert, Scott Bryant, Brian Bergeron, Landon Gilkey, Ben Keller, Bernard H. Guiot, Aizik Wolf, Matthew Philips, John T. Friedland
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Publication number: 20150137340Abstract: A secure integrated circuit package is provided. The secure integrated circuit package includes a first substrate having an upper surface and a lower surface. A first plurality of solder balls are arranged in a pattern on the lower surface of the first substrate. A die is coupled to the upper surface of the first substrate. A second plurality of solder balls is coupled to the upper surface of the substrate and arranged in a ring surrounding the die. A mesh substrate including a mesh protection grid is coupled to the second plurality of solder balls.Type: ApplicationFiled: November 13, 2014Publication date: May 21, 2015Inventors: Mark BUER, Matthew KAUFMANN
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Patent number: 8957516Abstract: A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.Type: GrantFiled: April 7, 2014Date of Patent: February 17, 2015Assignee: Broadcom CorporationInventors: Mengzhi Pang, Ken Zhonghua Wu, Matthew Kaufmann
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Patent number: 8890298Abstract: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.Type: GrantFiled: June 24, 2013Date of Patent: November 18, 2014Assignee: Broadcom CorporationInventors: Mark Buer, Matthew Kaufmann
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Publication number: 20140217573Abstract: A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.Type: ApplicationFiled: April 7, 2014Publication date: August 7, 2014Applicant: Broadcom CorporationInventors: Mengzhi PANG, Ken Zhonghua WU, Matthew KAUFMANN
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Patent number: 8749011Abstract: In one embodiment, a die arrangement is disclosed in which a wire-bond pad may be operatively coupled to a power supply via a wire bond. A first pad may be operatively coupled to the wire-bond pad. A second pad may be operatively coupled to the first pad via a redistribution layer.Type: GrantFiled: April 26, 2005Date of Patent: June 10, 2014Assignee: Broadcom CorporationInventors: Matthew Kaufmann, Morteza Cyrus Afghahi
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Publication number: 20140035136Abstract: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.Type: ApplicationFiled: June 24, 2013Publication date: February 6, 2014Inventors: Mark BUER, Matthew Kaufmann
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Patent number: 8508054Abstract: An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.Type: GrantFiled: June 16, 2011Date of Patent: August 13, 2013Assignee: Broadcom CorporationInventors: Mengzhi Pang, Matthew Kaufmann
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Patent number: 8502396Abstract: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.Type: GrantFiled: December 8, 2008Date of Patent: August 6, 2013Assignee: Broadcom CorporationInventors: Mark Buer, Matthew Kaufmann
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Publication number: 20130187284Abstract: A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.Type: ApplicationFiled: January 24, 2012Publication date: July 25, 2013Applicant: BROADCOM CORPORATIONInventors: Mengzhi Pang, Ken Zhonghua Wu, Matthew Kaufmann
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Publication number: 20120319269Abstract: An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Applicant: Broadcom CorporationInventors: Mengzhi Pang, Matthew Kaufmann
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Publication number: 20120256305Abstract: Embodiments of an integrated circuit package security fence are provided. The integrated circuit package includes a substrate, a die, and a security fence coupled to the substrate such that the die is located between the security fence and the substrate. The security fence includes a first signal net having a plurality of bonding wires and a second signal net having a second plurality of bonding wires. The bonding wires of the first signal net and second signal net are arranged in a pattern to overlap the top surface of die. The die may include tamper detection logic to detect attempt to access the die through the security fence.Type: ApplicationFiled: September 30, 2011Publication date: October 11, 2012Applicant: Broadcom CorporationInventors: Matthew Kaufmann, Mark Buer, Reza Sharifi
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Publication number: 20100153358Abstract: The invention disclosed herein is directed to a system and method for displaying graphics, text, video and other information and content. In one embodiment of the invention, the system comprises a web portal. The web portal may include one or more display windows, each of which is capable of displaying different content. Other features of the invention may include functionality which permits the uploading and downloading of content and statistical data gathering.Type: ApplicationFiled: September 1, 2009Publication date: June 17, 2010Inventors: David F. Itkoff, Matthew Kaufmann
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Publication number: 20090146270Abstract: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.Type: ApplicationFiled: December 8, 2008Publication date: June 11, 2009Applicant: Broadcom CorporationInventors: Mark BUER, Matthew Kaufmann
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Publication number: 20070139068Abstract: Forming a wafer level chip scale flip chip package includes determining isolation requirements of an integrated circuit formed in a semi conductive substrate from package signal connections of the wafer level chip scale flip chip package. Operation may further include, based upon the integrated circuit characteristics, selecting a thickness of at least one dielectric layer isolating a top metal layer of the integrated circuit from the package signal connections of the wafer level chip scale flip chip package, determining a minimum pitch of the package signal connections of the wafer level chip scale flip chip package, and determining a maximum lateral distance from the signal pad to a servicing package signal connection of the wafer level chip scale flip chip package and determining a position of the servicing package signal connection of the wafer level chip scale flip chip package based upon the maximum lateral distance.Type: ApplicationFiled: March 14, 2006Publication date: June 21, 2007Applicant: Broadcom Corporation, a California CorporationInventors: Arya Behzad, Matthew Kaufmann, Malcolm MacIntosh, Jacob Rael, Henry Chen
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Publication number: 20070102815Abstract: The present invention provides a simplified process end flow for a flip chip device. This process flow, beginning with the deposition of a final metal layer for the IC, also includes the deposition of the UBM layer on top of the metal layer. The UBM layer and IC final metal layer are simultaneously patterned. This ensures alignment between the IC final metal layer and the UBM layer patterning and reduces processing steps. Such a process flow may eliminate the need for a second passivation deposition and patterning and the process of individually patterning the final metal layer.Type: ApplicationFiled: November 8, 2005Publication date: May 10, 2007Inventors: Matthew Kaufmann, Ray Huang, Vincent Chen
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Publication number: 20060192297Abstract: In one embodiment, a die arrangement is disclosed in which a wire-bond pad may be operatively coupled to a power supply via a wire bond. A first pad may be operatively coupled to the wire-bond pad. A second pad may be operatively coupled to the first pad via a redistribution layer.Type: ApplicationFiled: April 26, 2005Publication date: August 31, 2006Inventors: Matthew Kaufmann, Morteza Afghahi