Abstract: A bit-error-rate detector (20) in a test set (10) for a frame-based communications channel employs a pseudo-random-number generator (46) at the channel's output end that generates a sequence the same as that produced by a pseudo-random-number generator (16) at the input end, but typically with a timing offset. A chain of delay circuits (38, 40, 42, and 44) receives the channel output. Each delay circuit imposes a delay equal to a single frame time and produces a respective output. One such output (CENTER) is normally compared in an XOR gate (52) with the output of the output-end pseudo-random-number generator (46). The XOR gate (52) applies signals indicative of any symbol mismatches to a shift register (88), which forwards them, after a delay, to a bit-error-rate counter (90).

Abstract: This disclosure is concerned with the automatic testing of electronic circuits and assemblies and the like containing large numbers of nodes, with reduced replications of test instruments and thus significantly reduced cost, through permitting a number of driver-sensors to be selectively switched to a larger number of nodes of the circuit being tested in accordance with a method of specifying and allocating the connections of the nodes of that circuit to the pins associated with each driver-sensor (or group thereof) that insures that no conflicts arise in connecting the driver-sensors to various groups of nodes for carrying out the desired tests.

Abstract: This disclosure is concerned with novel current-tracing of short circuits in printed circuit boards and similar systems by novel test excitation of the conductors with tracing of the phase polarities of the fields generated therein.