Patents by Inventor Matthew L. Tingey
Matthew L. Tingey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11676891Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: GrantFiled: June 30, 2021Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
-
Publication number: 20230022714Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: ApplicationFiled: September 29, 2022Publication date: January 26, 2023Inventors: Hongxia Feng, Dungying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
-
Publication number: 20210327800Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Inventors: Hongxia FENG, Dingying David XU, Sheng C. LI, Matthew L. TINGEY, Meizi JIAO, Chung Kwang Christopher TAN
-
Patent number: 11088062Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: GrantFiled: July 19, 2017Date of Patent: August 10, 2021Assignee: Intel CorporationInventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
-
Publication number: 20190027431Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: ApplicationFiled: July 19, 2017Publication date: January 24, 2019Inventors: Hongxia FENG, Dingying David XU, Sheng C. LI, Matthew L. TINGEY, Meizi JIAO, Chung Kwang Christopher TAN
-
Patent number: 9142421Abstract: Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.Type: GrantFiled: December 29, 2011Date of Patent: September 22, 2015Assignee: INTEL CORPORATIONInventors: Charles H. Wallace, Swaminathan Sivakumar, Matthew L. Tingey, Chanaka D. Munasinghe, Nadia M. Rahhal-Orabi
-
Publication number: 20140017899Abstract: Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.Type: ApplicationFiled: December 29, 2011Publication date: January 16, 2014Inventors: Charles H. Wallace, Swaminathan Sivakumar, Matthew L. Tingey, Chanaka D. Munasinghe, Nadia M. Rahhal-Orabi
-
Patent number: 8409690Abstract: Nanowires suspended from a substrate surface and methods of making nanowires suspended from a substrate surface are provided. The suspended nanowires are comprised of a variety of materials, including metals and mixtures of metals. Suspended nanowires supply large surface areas for applications such as, for example, energy storage and catalysis. Embodiments of the invention provide three dimensional nanowires attached to a substrate surface and arrays of three dimensional nanowires.Type: GrantFiled: May 7, 2010Date of Patent: April 2, 2013Assignee: Intel CorporationInventors: Charles H. Wallace, Matthew L. Tingey, Bradford L. Sun, Timothy L. Hehr
-
Patent number: 8133680Abstract: The present invention provides methods, devices and kits for detecting a ligand. The methods involve capturing a ligand from a sample with an affinity substrate that includes a receptor for a ligand, transferring captured ligand to a detection surface and detecting the ligand on the detection surface with a liquid crystal. Accordingly, the capture step is decoupled from the detection step.Type: GrantFiled: September 23, 2004Date of Patent: March 13, 2012Assignee: Wisconsin Alumni Research FoundationInventors: Nicholas L. Abbott, Matthew L. Tingey, Brian H. Clare, Chang-Hyun Jang
-
Publication number: 20110274882Abstract: Nanowires suspended from a substrate surface and methods of making nanowires suspended from a substrate surface are provided. The suspended nanowires are comprised of a variety of materials, including metals and mixtures of metals. Suspended nanowires supply large surface areas for applications such as, for example, energy storage and catalysis. Embodiments of the invention provide three dimensional nanowires attached to a substrate surface and arrays of three dimensional nanowires.Type: ApplicationFiled: May 7, 2010Publication date: November 10, 2011Inventors: Charles H. Wallace, Matthew L. Tingey, Bradford L. Sun, Timothy L. Hehr