Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions; and a branch predictor to predict a branch outcome for a given branch instruction as one of taken and not-taken, based on branch prediction state information indexed based on at least one property of the given branch instruction. In a static branch prediction mode of operation, the branch predictor predicts the branch outcome based on static values of the branch prediction state information set independent of actual branch outcomes of branch instructions which are executed by the processing circuitry while in the static branch prediction mode. The static values of the branch prediction state information are programmable.

Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions fetched from an instruction cache, an instruction prefetcher to speculatively prefetch instructions into the instruction cache, and a branch predictor having at least one branch prediction structure to store branch prediction data for predicting at least one branch property of an instruction fetched for processing by the processing circuitry. On prefetching of a given instruction into the instruction cache by the instruction prefetcher, the branch predictor is configured to perform a prefetch-triggered update of the branch prediction data based on information derived from the given instruction prefetched by the instruction prefetcher. This can help to improve performance, especially for workloads with a high branch density and large branch re-reference interval.

Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions fetched from an instruction cache, an instruction prefetcher to speculatively prefetch instructions into the instruction cache, and a branch predictor having at least one branch prediction structure to store branch prediction data for predicting at least one branch property of an instruction fetched for processing by the processing circuitry. On prefetching of a given instruction into the instruction cache by the instruction prefetcher, the branch predictor is configured to perform a prefetch-triggered update of the branch prediction data based on information derived from the given instruction prefetched by the instruction prefetcher. This can help to improve performance, especially for workloads with a high branch density and large branch re-reference interval.

Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions; and a branch predictor to predict a branch outcome for a given branch instruction as one of taken and not-taken, based on branch prediction state information indexed based on at least one property of the given branch instruction. In a static branch prediction mode of operation, the branch predictor predicts the branch outcome based on static values of the branch prediction state information set independent of actual branch outcomes of branch instructions which are executed by the processing circuitry while in the static branch prediction mode. The static values of the branch prediction state information are programmable.

Abstract: Data processing apparatus comprises a processor configured to execute instructions, the processor having a pipelined instruction fetching unit configured to fetch instructions from memory during a pipeline period of two or more processor clock cycles prior to execution of those instructions by the processor; exception logic configured to respond to a detected processing exception having an exception type selected from a plurality of exception types, by storing a current processor status and diverting program flow to an exception address dependent upon the exception type so as to control the instruction fetching unit to initiate fetching of an exception instruction at the exception address; and an exception cache configured to cache information, for at least one of the exception types, relating to execution of the exception instruction at the exception address corresponding to that exception type and to provide the cached information to the processor in response to detection of an exception of that exception t

Abstract: Data processing apparatus comprises a processor configured to execute instructions, the processor having a pipelined instruction fetching unit configured to fetch instructions from memory during a pipeline period of two or more processor clock cycles prior to execution of those instructions by the processor; exception logic configured to respond to a detected processing exception having an exception type selected from a plurality of exception types, by storing a current processor status and diverting program flow to an exception address dependent upon the exception type so as to control the instruction fetching unit to initiate fetching of an exception instruction at the exception address; and an exception cache configured to cache information, for at least one of the exception types, relating to execution of the exception instruction at the exception address corresponding to that exception type and to provide the cached information to the processor in response to detection of an exception of that exception t

Abstract: An instruction cache stores cacheable instructions for access by a processing circuitry, the instruction cache having a data storage comprising a plurality of cache lines and a tag storage comprising a plurality of tag entries, each cache line for storing instruction data specifying a plurality of cacheable instructions, and each tag entry for storing an address identifier for the instruction data stored in an associated cache line. The instruction cache including valid flag storage for identifying whether each cache line is valid. Instruction cache control circuitry is arranged to store within a selected cache line of the data storage the instruction data for a plurality of cacheable instructions as retrieved from memory, to store within the tag entry associated with that selected cache line the address identifier for that stored instruction data, and to identify that selected cache line as valid within the valid flag storage.

Abstract: A data processing apparatus and method, the apparatus including processing circuitry for executing a sequence of instructions, each instruction having an associated memory address and the sequence of instructions including cacheable instructions whose associated memory addresses are within a cacheable memory region. Instruction cache control circuitry is arranged to store within a selected cache line of a data storage the instruction data for a plurality of cacheable instructions as retrieved from memory, to store within the tag entry associated with that selected cache line the address identifier for that stored instruction data, and to identify that selected cache line as valid within the valid flag storage. Control state circuitry maintains a record of the chosen cache line in which said data of a predetermined data type has been written, so that upon receipt of a request for that data it can then be provided from the instruction cache.