Abstract: A system, apparatus and method is described for dynamically boosting (increasing) the power supply voltage to an envelope tracking (ET) modulator within a transmitter system when the target/desired power amplifier voltage supply is above a predetermined threshold (e.g., equal to the available power supply of the system, such as a battery). By boosting the power input supply to the ET modulator, the modulated power supply provided to the power amplifier (PA) is also increased. This reduces or eliminates clipping that normally occurs when the target/desired PA supply voltage is greater than the available power supply voltage and reduces distortion in the transmitted signal.

Abstract: A system, apparatus and method is described for dynamically boosting (increasing) the power supply voltage to an envelope tracking (ET) modulator within a transmitter system when the target/desired power amplifier voltage supply is above a predetermined threshold (e.g., equal to the available power supply of the system, such as a battery). By boosting the power input supply to the ET modulator, the modulated power supply provided to the power amplifier (PA) is also increased. This reduces or eliminates clipping that normally occurs when the target/desired PA supply voltage is greater than the available power supply voltage and reduces distortion in the transmitted signal.

Abstract: A system and method is disclosed for calibrating comparators of an ADC while the ADC continues to operate in an uninterrupted fashion. Groups (banks) of interleaved comparators may be calibrated at random or psuedo-random times while the ADC is performing conversions without the addition of extra “proxy” or replacement comparators. More particularly, at periodic intervals the comparators of one bank may be disconnected from the standard ADC circuitry for calibration or auto-zeroing while the comparators in the remaining bank(s) are left in the data conversion path. In order to prevent a significant degradation in the conversion quality, logic downstream of the comparators provides the necessary adjustments to accommodate for the removal of the comparators and outputs a word of the desired bit length. The multi-bank ADC is particularly advantageous for use with optical data storage systems.

Abstract: A system and method is disclosed for calibrating comparators of an ADC. Individual comparators may be calibrated at random or psuedo-random times while the ADC is performing conversions without the addition of extra "proxy" or replacement comparators. More particularly, at periodic intervals a psuedo-random one of the comparators may be disconnected from the standard ADC circuitry for calibration. In order to prevent a significant degradation in the conversion quality, the digital logic downstream of the comparators may be designed to provide the necessary adjustments to accommodate for the removal of one of the comparators. Thus, a calibration technique is provided in which individual comparators are removed from the data conversion path during conversion and the downstream logic adjusts to accommodate for the removal of the comparator. The calibration technique is particularly advantageous for use with optical data storage systems.

Abstract: A system and method for regulating the voltage at an input node of a varying current demand circuit is provided. The input node may be a power supply node and the varying current demand circuit may be a controllable oscillator. In addition, a frequency synthesizer may be formed from a phase locked loop which includes the controllable oscillator and a voltage control circuit. The voltage control circuit may receive an input control signal that varies as the current demand of the controllable oscillator varies. In response to the input control signal, the voltage control circuit may provide a more stable voltage supply to the controllable oscillator even as the current demands of the oscillator vary widely. The input control signal may be generated by generating a signal from the loop path of the phase locked loop. The frequency synthesizer may be utilized in a data storage system data detection circuit, such as for example, a data detection circuit used for recovering data from an optical disk.